JP2000055758A - Manufacture of semiconductor pressure sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the instability of stress due to a sealing member, by increasing the gap of etching liquid injection ports that is provided in either the <110> direction or <100> direction of a single crystal silicon substrate. SOLUTION: An N well region 5 is arranged on a P-well region 4 where the orientation face is (100) face for penetrating the N well region 5, and at the same time a trench 9 for injecting an etching liquid reaching a specific depth is provided at the lower P well region 4 with a specific gap in either the <110> or <100> direction of a single crystal silicon substrate. Then, a single crystal silicon substrate is etched by injecting an anisotropic etching liquid through the trench 9 for injecting the etching liquid, a cavity 7 where a side wall 7a is constituted by the face (111) whose width becomes narrower in upper and lower directions in a depthwise direction from the widest site is formed, and a through hole 8 and a penetration hole 9 are blocked by a sealing member 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor pressure sensor.

[0002]

2. Description of the Related Art Along with the recent miniaturization and high accuracy of a semiconductor sensor chip, a diaphragm serving as a sensing unit has been reduced in size, thickness, and accuracy. The applicant is Japanese Patent Application No. Hei 9
-295678 No.
A method for manufacturing a sensor having a thin diaphragm is proposed. The manufacturing method is to perform silicon anisotropic etching from micro holes arranged in an X-shape or cross on the surface of a silicon substrate to form a cavity serving as a reference pressure chamber, and then vacuum seal the micro holes. Then, the sensing unit is used.

More specifically, as shown in FIG. 24, a mask material 51 is arranged on a single-crystal silicon substrate 50 having a (100) plane orientation, and a large number of through-holes 52 formed in the mask material 51 are formed. The cavity 53 is formed by performing anisotropic etching on the silicon substrate 50 exposed through the through hole. The silicon anisotropic etching at this time proceeds as follows.

First, the silicon substrate 50 exposed from the through hole 52 of the mask material 51 is etched to form a cavity 54 having a V-shaped cross section indicated by a solid line in FIG.
The point P10 on the side wall of the cavity 54 moves to P11 as indicated by a dashed line due to the progress of etching, and a cavity 55 having a V-shaped cross section is formed. Then, the ends of the adjacent V-shaped cavities 55 overlap with each other, and this overlapping portion P2
The etching proceeds downward from 0, and finally (11
1) A cavity 53 having a V-shaped cross section and a rectangular plane is formed by stopping at the plane.

[0005] As described above, there is a corner drop process of the (311) plane going from point P10 to point P11 and a corner drop process of the (311) surface going downward from point P20.
In this manufacturing method, the ends of the adjacent V-shaped cavities 55 need to overlap and communicate with each other, so that the interval W between the adjacent through holes 52 also needs to be very small. The through-hole 52 is sealed. However, since a material other than silicon is used as a material for vacuum sealing, a complicated stress distribution is generated in the diaphragm serving as the sensing unit, and the sealing is performed. It has an unstable element due to the shape. As a result, the pressure characteristics of the sensor tend to be unstable.

[0006]

Therefore, an object of the present invention is to provide a single crystal silicon substrate in the <110> direction or <1> direction.
It is an object of the present invention to provide a method of manufacturing a semiconductor pressure sensor capable of avoiding instability of stress caused by a sealing member by widening an interval between etching solution injection ports arranged in parallel in the <00> direction.

[0007]

According to the method of manufacturing a semiconductor pressure sensor according to the present invention, the plane orientation of the surface is (10).
A diaphragm forming material is arranged on the single crystal silicon substrate on the 0) plane. Etching solution injection trenches penetrating the diaphragm forming material and reaching a predetermined depth in the single crystal silicon substrate thereunder are formed at predetermined intervals in the <110> direction or the <100> direction of the single crystal silicon substrate. And are juxtaposed. Further, the single crystal silicon substrate is etched by the injection of the anisotropic etching solution through the etching solution injection trench, and the width of the side wall becomes narrower in the depth direction from the widest portion to the vertical direction (111). A cavity composed of surfaces is formed. Finally, the through hole of the diaphragm forming material is closed by the sealing member.

[0008] A mechanism relating to silicon etching during this manufacturing will be described with reference to FIG. 23 instead of FIG. 24. A mask material 51 is disposed on a silicon substrate 50, and the silicon substrate 50 under a through-hole 52 formed in the mask material 51.
When a trench 56 is formed in the trench 56 and anisotropic etching is performed through the trench 56, the point P1 on the side wall of the trench 56 shown by a solid line moves to P2 as shown by a one-dot chain line as the etching proceeds, and the cross-sectional shape becomes Diamond-shaped cavity 55
Becomes Then, the tips of the adjacent rhombic cavities 55 overlap with each other, and the etching progresses vertically from this overlapping portion P3, and the cavities 5 each have a rhombic cross section and a square planar shape.
3 is formed.

Here, when the depth of the trench 56 is "D", the interval between the through hole 52 and the trench 56 is "W", and the width of the through hole 52 and the trench 56 is "a", the relationship is as follows. = A + 2D, the distal ends of the cavities 55 can communicate with each other as shown in FIG.

That is, if the D value which is the depth of the trench 56 is increased, the distance W between the through hole and the trench can be increased. Therefore, in the comparative example of FIG. 24, if the a value is constant, the W value is uniquely determined. However, in the present method of FIG. 23, even when the a value is constant, the W value is increased by increasing the trench depth D. The value can be increased.

As described above, by adopting the manufacturing method shown in FIG. 23 in which a trench etching step is added to the manufacturing method shown in FIG. 24 as a method for manufacturing a diaphragm serving as a sensing portion, the distance between adjacent through holes can be increased. In addition, the number of sealing portions of the through holes can be reduced. As a result, a structure in which stress is not easily applied can be achieved, and high precision of the pressure characteristics can be achieved.

As described above, the single crystal silicon substrate <1
The instability of the stress due to the sealing member can be avoided by increasing the interval between the etching solution injection ports arranged in parallel in the 10> direction or the <100> direction.

Here, the first conductive type impurity diffusion region and the second conductive type impurity diffusion region are formed on the surface layer of the single crystal silicon substrate having the (100) plane orientation. Forming a double diffusion region composed of an impurity diffusion region and an etching solution injection trench penetrating the impurity diffusion region on the upper side of the double diffusion region and reaching a predetermined depth thereunder; Anisotropic etching is performed in a state where a potential difference is generated between the impurity diffusion region of the first conductivity type and the impurity diffusion region of the second conductivity type of the heavy diffusion region, and the etching is stopped at the PN junction interface. Alternatively, a trench for etching solution injection is formed in a silicon substrate disposed on a substrate with a buried oxide film interposed therebetween, and anisotropic etching is performed to perform etching with the buried oxide film. To stop Or through the upper silicon substrate and the buried oxide film of the bonded substrate obtained by bonding the silicon substrate to the silicon substrate via the buried oxide film as described in claim 4; A trench for injecting an etchant reaching a predetermined depth is formed in the silicon substrate, and anisotropic etching is performed on the lower silicon substrate so that the etching is stopped by the buried oxide film. This is practically preferable.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor pressure sensor according to the present embodiment, in which an upper side shows a plane and a lower side shows an A-A cross section thereof. More specifically,
This shows a state after dicing is performed on each chip from a wafer state. In addition, the upper plan view shows the trench etching mask 6 in the AA sectional view for easy understanding.
And a state where the sealing member 10 is removed.

On the silicon substrate 1, an N-type silicon substrate 3 is bonded via a buried oxide film (bonding oxide film) 2. This silicon substrate 3 is thinned to a thickness of about 15 μm to form an SOI layer. As the silicon substrate 3, a silicon substrate having a (100) plane orientation is used. In the center of the SOI layer 3, a double diffusion region of a deep P well region 4 and a shallow N well region 5 is formed in the surface layer. The planar shape of the double diffusion regions 4 and 5 is a quadrangle.

A trench etching mask 6 is formed on SOI layer 3, and trench etching mask 6 has a large number of through holes 8. N-well region 5 in SOI layer 3
Is formed with a through hole 9 having the same shape and the same size as the through hole 8.
Cavity 7 is formed between N well region 5 and buried oxide film 2 in SOI layer 3. The cavity 7 is formed by anisotropic etching of silicon by introducing an etching solution through the through holes 8 and the through holes 9. More specifically, the cavity 7 is formed at the interface between the P well region 4 and the N well region 5. This is formed by so-called electrochemical stop etching for stopping the etching. One shape of the through hole 8 and the through hole 9 is a square shape, and the entire arrangement of each through hole 8 and the through hole 9 is as follows.
<110> direction or <100> of single crystal silicon substrate 3
> Are arranged side by side at predetermined intervals in the direction.

The cavity 7 has a rectangular shape as a plane shape, and has a vertical cross-section having a maximum width at a predetermined position in the depth direction, and gradually narrows at the upper and lower sides. As described above, the cavity 7 has the upper surface formed at the PN interface, the lower surface formed by the buried oxide film 2, and the side wall 7a having the shape of a square.

A diaphragm 11 is formed in the N-well region 5 above the cavity 7. Further, the through hole 8 and the through hole 9 are closed by the sealing member 10, and the inside of the cavity 7 is evacuated. In this way, the inside of the cavity 7 becomes a vacuum chamber and serves as a reference pressure chamber in the absolute pressure sensor.

In the N-well region 5 constituting the diaphragm 11, four P-type impurity diffusion regions (piezoresistive elements) 12a, 12b, 12c and 12d are formed as gauge resistors. These four gauge resistors 12a to 12d
A Wheatstone bridge is configured.

In the sensor chip shown in FIG. 1, an integrated circuit portion 13 is formed on the outer peripheral side of the diaphragm 11, and the output signal of the Wheatstone bridge is amplified in the integrated circuit portion 13. Further, a large number of bonding pads 14 are provided in the peripheral portion of the sensor chip, and application of a predetermined potential, extraction of signals, and the like are performed by the pads 14.

Next, a method of manufacturing the semiconductor pressure sensor thus configured will be described with reference to FIGS. As shown in FIG. 2, an N-type single crystal silicon substrate 3 having a (100) plane orientation is bonded on a silicon substrate 1 via a buried oxide film (bonding oxide film) 2. Further, the silicon substrate 3 is thinned to about 15 μm by polishing or the like. In the SOI layer 3 of this SOI wafer, a double diffusion region of a P well region 4 and an N well region 5 is formed. P
The well region 4 and the N well region 5 are formed by using a general semiconductor manufacturing method such as photolithography, ion implantation, or diffusion.

The gauge resistors 12a to 12d and the integrated circuit section 13 are applied to the SOI layer 3 of the SOI wafer.
(FIG. 1) is formed by a general semiconductor manufacturing method. Subsequently, as shown in FIG. 3, a trench etching mask 6 is formed on the SOI layer 3. The mask material 6 is made of a material that can serve as a mask at the time of trench etching (dry etching of silicon), for example, a SiN-based film or a SiO ₂ -based film. Further, as shown in FIG. 7, the film 6 is patterned to arrange square through holes 8 in an X shape (or cross shape). That is, the through holes 8 are arranged side by side at predetermined intervals in the <110> direction or the <100> direction of the single crystal silicon substrate.

Further, as shown in FIG. 4, trench etching is performed on SOI layer 3 to form trench 9 reaching buried oxide film 2. As the etching method, dry etching of general silicon is used. For example, as shown by a solid line in FIG. 8, RIE (reactive ion etching) in which the angle of the side wall is substantially perpendicular to the substrate surface is used.

As shown by a chain line in FIG. 8, etching or the like may be performed so that the trench side wall has a forward taper. The trench 9 does not necessarily have to reach the buried oxide film 2.

Then, as shown in FIG. 5, by immersing in a wet etching solution,
The OI layer 3 is etched to form a cavity 7. In performing this etching, electrochemical stop etching is used. That is, a positive potential is applied to the N well region 5 and an arbitrary potential is applied to the P well region 4 (or floating). Thus, when the etching proceeds to the vicinity of the PN junction, an anodic oxide film is generated, and the etching is stopped. Using this electrochemical stop etching, the etching is stopped near the interface of the N-well region 5, whereby the N-well region 5
The diaphragm 11 is formed.

Here, the reason that the vicinity of the interface between the N well regions 5 is described is that, in the method by the electrochemical stop etching, the two well regions 4 and 5 are formed at the PN junction between the N well region 5 and the P well region 4. This is because the depletion layer is expanded and the etching is stopped, so that the portion of the P well region 4 where the depletion layer is expanded remains. The remaining amount varies depending on the well concentration and the voltage application condition, but is about 0.2 to 0.3 μm.

The side wall 7a of the cavity 7 is stopped at the (111) plane due to the anisotropic etching characteristics of silicon, and is formed in a "<" shape. In addition, since the bottom surface of the cavity 7 has the buried oxide film 2, the etching is stopped at the oxide film 2 and formed.

As an etching solution, an alkaline etching solution having selectivity with respect to the mask material 6 is used. In particular,
For example, KOH is used, or TMAH (tetramethylammonium hydroxide) or the like is used when there is a concern about contamination of a surface circuit or a manufacturing apparatus.

Subsequently, as shown in FIG.
The film which becomes 0 is formed, and the through hole 8 and the through hole (trench) are formed.
9 is closed, and the cavity 7 is vacuum-sealed to form a reference pressure chamber. Specifically, a film is formed using a plasma CVD method, a low pressure CVD method, or the like, and patterning is performed. Thus, FIG.
Are manufactured.

Next, the superiority of the present embodiment will be described by comparing the manufacturing method in the present embodiment shown in FIGS. 9 and 10 with the manufacturing method in the comparative example shown in FIGS. Here, the drawing scales of FIGS. 9 and 10 and the drawing scales of FIGS. 11 and 12 are equal.

In FIG. 11, which is a comparative example, a patterned mask 6 is arranged on an SOI layer (bonded substrate) 3, and the SOI layer 3 is etched as shown in FIG.
At this time, the interval W between the through holes 8 in the mask 6 is set to a predetermined value. In this case, the inverted quadrangular pyramid 17 having the (111) plane is used.
Etching is stopped in a state where is formed. In other words, the interval W between the through holes 8 is simply a diamond pattern formed by the corners of the square through holes 8 when only the mask pattern (in this embodiment, the N well region 5 of the diaphragm also serves as an etching mask). If the W value is not smaller than the length a ′ of the diagonal line, the adjacent inverted quadrangular pyramid 17 does not connect and the etching does not proceed.

On the other hand, a patterned mask 6 is arranged on the SOI layer 3 in FIG. 9, and the SOI layer 3 is dry-etched to form a trench 9. At this time, the interval W between the through holes 8 in the mask 6 is set to the same value as in the case of FIG. From this state, anisotropic etching of silicon is performed as shown in FIG. As the etching progresses, a rhombic cavity 16 is formed as a cross-sectional shape, and the end surfaces of adjacent rhombic cavities 16 communicate with each other at a predetermined depth (connect). Thereafter, the etching is continuously performed, and the cavity 7 serving as the reference pressure chamber can be formed.

In this case, referring to the depth of the trench 9, the diameter and the interval of the trench 9 in FIG.
Is "a", the interval (pitch) between the trenches 9 is "W", and the depth of the trench 9 is "D".
When a + 2D is satisfied, the distal ends of the rhombic cavities 16 can communicate with each other as shown in FIG. For example, if D = 10 μm and a = 5 μm, W
= 25 μm.

In other words, the method shown in FIG.
As can be seen from the comparative example shown in FIG. 1, when the positions of the through holes 8 of the mask 6 are determined so that the inverted quadrangular pyramids 17 of FIG. 12 communicate with each other in the initial stage of the silicon etching, and the cavities 16 of FIG. In the comparative example, the pitch W of the through holes 8
Must be narrowed, and the number of through holes 8 for manufacturing a reference pressure chamber having the same area increases. On the other hand, by adding the trench forming step of FIG. 9 as in the present embodiment, the number of the through holes 8 of the mask 6 for manufacturing the reference pressure chamber having the same area can be reduced.

Further, since the trench processing reaches the buried oxide film 2, the interval between the trenches can be made wider, and after the ends of the cavities 16 communicate with each other as shown in FIG. As shown in (1), the corner drop of the (311) plane progresses, and the etching is finally stopped to form the above-described cavity (reference pressure chamber) 7.

When the semiconductor pressure sensor is manufactured in this manner, the distance between the adjacent through holes 8 can be increased, and the sealing member 10 which adversely affects the sensing characteristics can be reduced. As a result, unstable elements of the sealing shape are reduced, and the sensing characteristics can be further improved.

As described above, this embodiment has the following features. (A) As shown in FIG. 2, on a P-well region 4 as a single crystal silicon substrate having a (100) plane orientation,
An N-well region 5 as a diaphragm forming material is arranged,
As shown in FIG. 4, a trench 9 for injecting an etchant penetrating the N-well region 5 and reaching a predetermined depth in the P-well region 4 therebelow is formed in the <11 of the single-crystal silicon substrate.
They are arranged side by side at predetermined intervals in the 0> direction or the <100> direction. Then, as shown in FIG. 5, the single crystal silicon substrate 3 is etched by injecting an anisotropic etching solution through the etching solution injecting trench 9, and the side wall 7a is removed.
A cavity 7 composed of a (111) plane whose width decreases in the vertical direction in the depth direction from the widest portion is formed, and as shown in FIG. 6, the through hole 9 of the diaphragm forming material is formed.
Is closed by the sealing member 10. Therefore, the interval between the trenches can be widened, the location of the sealing member 10 can be reduced, and a structure in which stress is hardly applied can be obtained. As a result, the <110> direction or <1>
The instability of the stress caused by the sealing member 10 can be avoided by increasing the interval between the etching solution injection ports arranged in parallel in the <00> direction. (B) More specifically, as shown in FIG. 2, the surface layer of the single crystal silicon substrate 3 having the (100) plane orientation is
A double diffusion region comprising a P-type impurity diffusion region 4 and an N-type impurity diffusion region 5 is formed, and penetrates the upper N-type impurity diffusion region 5 in the double diffusion region as shown in FIG. In addition, an etching solution injection trench 9 reaching a predetermined depth is formed thereunder, and a potential difference between the P-type impurity diffusion region 4 and the N-type impurity diffusion region 5 is formed as shown in FIG. Since the anisotropic etching is performed in this state and the etching is stopped at the PN junction interface, it is practically preferable. (C) Further, as shown in FIG. 4, an etching solution injection trench 9 is formed in the silicon substrate 3 disposed on the substrate 1 with the buried oxide film 2 interposed therebetween, and as shown in FIG. Since the isotropic etching is performed to stop the etching at the buried oxide film 2, this is practically preferable. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

FIGS. 15 to 22 show the steps of manufacturing the semiconductor pressure sensor according to the present embodiment. In this example, FIG.
As shown in FIG.
A cavity (reference pressure chamber) 24 is formed, and a diaphragm is formed by the silicon layer 3 thereon.
Further, at the time of etching for forming the cavity (reference pressure chamber) 24, etching is performed for a predetermined time by time-controlled etching without using electrochemical stop etching. At this time, a buried oxide film (bonded oxide film) 2 is used as an etching mask for the diaphragm.

The details will be described below. First, as shown in FIG. 15, a silicon substrate 3 is bonded via an oxide film 2 on a single crystal silicon substrate 1 having a (100) plane orientation, and the silicon substrate 3 is ground and polished to form a thin film. Become Then, the gauge resistors 12a to 12d and the integrated circuit section 13 are formed on the SOI layer 3 of the bonded substrate (SOI substrate), and the mask material 6 is deposited and patterned as shown in FIG. And, as shown in FIG.
The trench etching of the SOI layer 3 is performed, and the buried oxide film 2 is formed.
Is formed, and as shown in FIG.
An oxide film 21 is formed on the side wall of the trench 20. further,
As shown in FIG. 19, the buried oxide film 2 on the bottom surface of the trench 20 is removed by etching to form a through hole 22.

Then, as shown in FIG. 20, the silicon substrate 1 is subjected to trench etching to form a trench 23 having a predetermined depth. The trenches 23 are juxtaposed at predetermined intervals in the <110> direction or the <100> direction of the single crystal silicon substrate. Then, as shown in FIG. 21, a cavity 24 is formed by performing anisotropic etching on the silicon substrate 1. At this time, the etching is completed by time management. At this time, the side wall of the trench 20 is protected from the etchant by the oxide film 21. Finally, as shown in FIG. 22, the through holes 8, 22 and the trench 20 are closed with a sealing member 25.

As described above, this embodiment has the following features. (A) As shown in FIG. 20, the upper silicon substrate 3 and the buried oxide film 2 of the bonded substrate in which the silicon substrate 3 is bonded to the silicon substrate 1 via the buried oxide film 2 are penetrated, Etching solution injection trenches (20, 22, 23) reaching a predetermined depth are formed in lower silicon substrate 1, and anisotropic etching is performed on lower silicon substrate 1 to etch with buried oxide film 2. Is stopped, which is practically preferable.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor pressure sensor according to an embodiment.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 4 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 7 is a plan view showing a mask pattern.

FIG. 8 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 9 is a cross-sectional view for explaining a manufacturing process.

FIG. 10 is an explanatory diagram for explaining a manufacturing process.

FIG. 11 is a cross-sectional view for explaining a manufacturing process in a comparative example.

FIG. 12 is an explanatory diagram for explaining a manufacturing process in a comparative example.

FIG. 13 is an explanatory diagram for explaining a manufacturing process.

FIG. 14 is an explanatory diagram for explaining a manufacturing process in a comparative example.

FIG. 15 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 16 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 17 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 18 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 19 is a sectional view for explaining the manufacturing process of the semiconductor pressure sensor.

FIG. 20 is a sectional view for explaining the manufacturing process of the semiconductor pressure sensor.

FIG. 21 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 22 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 23 is a diagram showing a plane and a cross section for explaining a process of the present invention.

FIG. 24 is a diagram showing a plane and a cross section for explaining a process of the prior art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Buried oxide film, 3 ... SOI layer, 4
... P-well region, 5 ... N-well region, 7 ... hollow, 7a ...
Side wall, 9: through hole, 10: sealing member

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2F055 AA40 BB20 CC02 DD05 EE14 FF15 FF23 GG01 GG11 4M112 AA01 BA01 CA03 CA05 CA16 DA04 DA12 EA03 5F043 AA02 BB02 DD14 DD15 DD30 FF01 FF10 GG06 GG10

Claims (4)

[Claims] A step of arranging a diaphragm forming material on a single crystal silicon substrate having a (100) plane orientation on a surface; and a step of penetrating the diaphragm forming material and applying a predetermined amount to a single crystal silicon substrate thereunder. Arranging trenches for injecting an etchant reaching the depth at predetermined intervals in the <110> direction or <100> direction of the single crystal silicon substrate; Etching the single-crystal silicon substrate by injecting an etchant to form a cavity having a (111) plane in which a side wall is narrower in a vertical direction in a depth direction from a widest part; Closing the through hole of the diaphragm forming material with a sealing member. 2. A double diffusion region comprising a first conductivity type impurity diffusion region and a second conductivity type impurity diffusion region in a surface layer portion of a single crystal silicon substrate having a surface orientation of a (100) plane. Is formed, penetrating the impurity diffusion region on the upper side of the double diffusion region, and forming a trench for injecting an etchant reaching a predetermined depth below the impurity diffusion region, and forming a first conductivity type of the double diffusion region. 2. The semiconductor pressure sensor according to claim 1, wherein anisotropic etching is performed in a state where a potential difference is generated between the impurity diffusion region and the second conductivity type impurity diffusion region, and the etching is stopped at a PN junction interface. Manufacturing method. 3. A method according to claim 1, wherein a trench for injecting an etching solution is formed in a silicon substrate disposed on the substrate via a buried oxide film, and anisotropic etching is performed to stop the etching at the buried oxide film. Item 2. A method for manufacturing a semiconductor pressure sensor according to Item 1. 4. A bonded substrate, in which a silicon substrate is bonded via a buried oxide film on a silicon substrate, penetrates an upper silicon substrate and a buried oxide film, and has a predetermined depth in a lower silicon substrate. 2. The method for manufacturing a semiconductor pressure sensor according to claim 1, wherein a trench for injecting an etching solution is formed to reach an upper limit, and anisotropic etching is performed on the lower silicon substrate to stop the etching at the buried oxide film.