JPH01170054A - Manufacture of semiconductor pressure sensor - Google Patents
Manufacture of semiconductor pressure sensorInfo
- Publication number
- JPH01170054A JPH01170054A JP32901887A JP32901887A JPH01170054A JP H01170054 A JPH01170054 A JP H01170054A JP 32901887 A JP32901887 A JP 32901887A JP 32901887 A JP32901887 A JP 32901887A JP H01170054 A JPH01170054 A JP H01170054A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- buried layer
- strain
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 238000005259 measurement Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 14
- 238000000866 electrolytic etching Methods 0.000 abstract description 9
- 239000007788 liquid Substances 0.000 abstract 1
- 238000004891 communication Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、シリコンなどの半導体結晶の持つピエゾ抵抗
効果などを利用して圧力を電気信号に変換する圧力セン
サの製造方法に係り、特にそのダイアプラムの製造方法
を改良した半導体圧力センサの製造方法に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for manufacturing a pressure sensor that converts pressure into an electrical signal by utilizing the piezoresistance effect of semiconductor crystals such as silicon, and in particular, The present invention relates to a method for manufacturing a semiconductor pressure sensor that is an improved method for manufacturing a diaphragm.
く従来の技術〉
第2図は従来の半導体圧力センサの構成を示す構成図で
ある。2. Prior Art> FIG. 2 is a block diagram showing the structure of a conventional semiconductor pressure sensor.
第2図(イ)は半導体圧力センサの平面図、1(ロ)は
半導体圧力センサの横断面図を示す、1はn形のシリコ
ン単結晶で作られたダイヤフラムであり、凹部2を有し
更に凹部2の形成により単結晶の厚さの薄くなった起歪
部3とその周辺の固定部4とを有している。Figure 2 (A) is a plan view of the semiconductor pressure sensor, and Figure 1 (B) is a cross-sectional view of the semiconductor pressure sensor. Furthermore, it has a strain-generating part 3 in which the thickness of the single crystal is reduced due to the formation of the recessed part 2, and a fixing part 4 around the strain-generating part 3.
固定部4は連通孔5を有する基板6にガラス薄fi7を
介して陽極接合などにより固定されている。The fixing part 4 is fixed to a substrate 6 having a communication hole 5 through a thin glass film 7 by anodic bonding or the like.
起歪部3は単結晶の(100)面とされ、その上にはそ
の中心を通る結晶軸<001>方向で起歪部3と固定部
4との境界付近に例えば剪断形ゲージなどの感圧素子8
が不純物の拡散により伝導形がP形として矩形状に形成
されている。The strain-generating portion 3 is a (100) plane of a single crystal, and a sensor such as a shear type gauge is placed on the surface near the boundary between the strain-generating portion 3 and the fixed portion 4 in the <001> direction of the crystal axis passing through its center. Pressure element 8
is formed into a rectangular shape with the conductivity type being P type due to the diffusion of impurities.
この感圧素子8はその長手方向に電源端(図示せず)が
形成され、ここに電圧或いは電流が印加される。印加圧
力Pがダイヤフラム1に与えられると、これによって生
じた例えば剪断応力τに対応した電圧が感圧素子8の長
手方向のほぼ中央に形成された出力端(図示せず)に得
られる。This pressure sensitive element 8 has a power source end (not shown) formed in its longitudinal direction, to which a voltage or current is applied. When an applied pressure P is applied to the diaphragm 1, a voltage corresponding to, for example, shear stress τ generated thereby is obtained at an output end (not shown) formed approximately in the longitudinal center of the pressure sensitive element 8.
これによって、印加圧力Pに対応した電圧が出力端に得
られる。As a result, a voltage corresponding to the applied pressure P is obtained at the output end.
ところで、この様なダイアフラムを製造するには各種の
方法があるが、一般には(a)等方性のケミカルエツチ
ングにより製造するか(b)異方性のケミカルエツチン
グにより製造するかの方法がとられるが、このほかに(
c)n”シリコン基板にn形のエピタキシャル層を積み
n形のエピタキシャル層をエツチングストップ層として
電解エツチングによりn1シリコン基板に孔開けをする
製造方法もある。By the way, there are various methods for manufacturing such a diaphragm, but generally there are two methods: (a) manufacturing by isotropic chemical etching, and (b) manufacturing by anisotropic chemical etching. However, in addition to this (
c) There is also a manufacturing method in which an n-type epitaxial layer is stacked on an n'' silicon substrate, and a hole is formed in the n1 silicon substrate by electrolytic etching using the n-type epitaxial layer as an etching stop layer.
〈発明が解決しようとする問題点〉
しかしながら、この様な従来の半導体圧力センサの製造
方法は以下に説明するような問題がある。<Problems to be Solved by the Invention> However, such a conventional method for manufacturing a semiconductor pressure sensor has the following problems.
(イ)第1の製造方法(a)によりダイアフラムの凹部
の加工を行うとその寸法精度を出すことが容易ではなく
、シリコンの中の不純物の濃度差を利用したエツチング
ストップ層を設けてダイアフラムの厚さを制御する方式
を採用しても半径方向の寸法精度が悪く、
(ロ)第2の製造方法(b)によりダイアフラム゛の凹
部の加工を行う場合は寸法精度は良いが、ダイアフラム
の起歪部の形状が4角形、8角形などに限定され、面と
面とが交差するところに角部が出来てこの部分に応力集
中が作用し高応力下での使用が難しく、
(ハ)第3の製造方法(C)によりダイアフラムの凹部
の加工を行う場合は高濃度のn+シリコン基板が入手し
難く、またダイアフラムの凹部の半径方向の寸法精度が
充分でない、
などの問題がある。(b) When processing the concave portion of the diaphragm using the first manufacturing method (a), it is not easy to achieve dimensional accuracy. Even if a method for controlling the thickness is adopted, the dimensional accuracy in the radial direction is poor. The shape of the strained part is limited to quadrangles, octagons, etc., and corners are formed where surfaces intersect, stress concentration acts on these parts, making it difficult to use under high stress. When processing the concave portion of the diaphragm using the manufacturing method (C) of No. 3, there are problems such as it is difficult to obtain a high concentration n+ silicon substrate, and the dimensional accuracy of the concave portion of the diaphragm in the radial direction is not sufficient.
く問題点を解決するための手段〉
この発明は、以上の問題点を解決するために、測定圧力
により変位する起歪部の形にパターニングされた高濃度
のn形シリコンの埋込み層を片方の面に持つp形シリコ
ン基板の前記埋込み層の上にエピタキシャル成長をさせ
てn形エピタキシャル層を形成し、さらにこの上にP形
のゲージを形成した後、異方性エツチングにより埋込み
層の深さまでp形シリコン基板の埋め込み層に対応する
部分に凹部を形成し、p形シリコン基板とn形エピタキ
シャル層との間に逆バイアス電圧を印加した状態でエツ
チング液に対してn形エピタキシャル層を正電位に保持
して埋込み層を電解エツチングして除去し起歪部を形成
するようにしたものである。Means for Solving the Problems> In order to solve the above problems, the present invention has a buried layer of high concentration n-type silicon patterned in the shape of a strain-generating portion that is displaced by measurement pressure. An n-type epitaxial layer is formed by epitaxial growth on the buried layer of the p-type silicon substrate held on the surface, and a P-type gauge is further formed on this layer, and then p-type is etched to the depth of the buried layer by anisotropic etching. A recess is formed in a portion of the silicon substrate corresponding to the buried layer, and the n-type epitaxial layer is brought to a positive potential with respect to the etching solution while applying a reverse bias voltage between the p-type silicon substrate and the n-type epitaxial layer. The buried layer is retained and removed by electrolytic etching to form a strain-generating portion.
く作 用〉
P形シリコン基板に高濃度のn形、の埋込み層を形成し
てこの上にさらにn形のエピタキシャル層を成長させて
ここにゲージを作り、この後p形シリコン基板に異方性
エツチングによりこの埋込み層に通じる凹部を形成し、
さらにP形シリコン基板とn形エピタキシャル層との間
に逆バイアス電圧を印加した状態でエツチング液に対し
てn形エピタキシャル層を正電位に保持して埋込み層を
電解エツチングして除去し起歪部を形成する。Function> A highly concentrated n-type buried layer is formed on a p-type silicon substrate, an n-type epitaxial layer is grown on top of this to form a gauge, and then an anisotropic layer is formed on the p-type silicon substrate. A recess leading to this buried layer is formed by etching,
Furthermore, with a reverse bias voltage applied between the P-type silicon substrate and the n-type epitaxial layer, the n-type epitaxial layer is held at a positive potential with respect to the etching solution, and the buried layer is electrolytically etched and removed. form.
〈実施例〉
以下、本発明の実施例について図面に基づいて説明する
。<Example> Hereinafter, an example of the present invention will be described based on the drawings.
第1図(イ)はp形のウェハ状のシリコン基板10に外
形が円形パターンになるようにn形の不純物を高濃度(
n+)で拡散して埋込みN11を形成する拡散工程を示
す。FIG. 1(a) shows a p-type wafer-shaped silicon substrate 10 doped with n-type impurities at a high concentration (
A diffusion process for forming a buried N11 by diffusing N+) is shown.
この拡散工程で形成された埋込み層の上に第1図(ロ)
に示す様にn形のエピタキシャル成長を行いn形エピタ
キシャル層12を形成する。On the buried layer formed by this diffusion process, as shown in FIG.
An n-type epitaxial layer 12 is formed by performing n-type epitaxial growth as shown in FIG.
第1図(ハ)のゲージ形成工程では、この第1図(ロ)
で形成されたエピタキシャル層12の上にp形のゲージ
13を拡散などにより形成し、その上を窒化膜などの絶
縁膜14で覆ってゲージ13を保護すると共にシリコン
基板10の底面を同様に窒化膜などの絶縁WA15で覆
い、次の異方性エツチング工程でのマスクとする。In the gauge forming process of Fig. 1 (c), this Fig. 1 (b)
A p-type gauge 13 is formed by diffusion or the like on the epitaxial layer 12 formed by the process, and is covered with an insulating film 14 such as a nitride film to protect the gauge 13, and the bottom surface of the silicon substrate 10 is also nitrided. It is covered with an insulating WA film 15 and used as a mask for the next anisotropic etching process.
この工程では、さらに後工程の準備としてn形エピタキ
シャル層12にn+の電極16を形成しておく。In this step, an n+ electrode 16 is formed on the n-type epitaxial layer 12 in preparation for a subsequent step.
第1図(ニ)は、異方性エツチングの工程を示す、この
工程では埋込み層11に対応するシリコン基板10の連
通孔17を作る部分の絶縁膜15を四角形にパターンニ
ングして開口し、n◆の堰込み層11をエッチストップ
面として水酸化カリウム(KOH)のエツチング液を用
いて異方性エツチングを行い、シリコン基板10に断面
が矩形の連通孔17を形成する。FIG. 1(D) shows the anisotropic etching process. In this process, the insulating film 15 is patterned into a rectangular shape and opened in a portion of the silicon substrate 10 corresponding to the buried layer 11 where a communication hole 17 is to be made. Anisotropic etching is performed using an etching solution of potassium hydroxide (KOH) using the n♦ dipping layer 11 as an etch stop surface to form a communicating hole 17 having a rectangular cross section in the silicon substrate 10.
第1図(ホ)は電解エツチングの工程を示す。FIG. 1(e) shows the electrolytic etching process.
この工程では、電極16を介してn形エピタキシャル層
12とp形のシリコン基板10との間に逆バイアスの直
流電圧E1とE2を印加し、さらに弗化水素(HF)又
は弗化アンモニウムなどのエツチング液の中に白金の電
極18を設けてこの電[!18を(−)極、n形エピタ
キシャル層12を(+)極として直流電圧E、を印加し
て等方性の電解エツチングを行う。In this step, reverse bias DC voltages E1 and E2 are applied between the n-type epitaxial layer 12 and the p-type silicon substrate 10 via the electrode 16, and hydrogen fluoride (HF) or ammonium fluoride, etc. A platinum electrode 18 is provided in the etching solution, and this electrode [! Isotropic electrolytic etching is performed by applying a DC voltage E with 18 as the (-) pole and the n-type epitaxial layer 12 as the (+) pole.
この電解エツチングにより、n+形の埋込み層11がエ
ツチングされて円形の凹部19とされ、この凹部19に
対向するn形エピタキシャル層12の部分が円形の起歪
部20となる第1図(へ)に示すダイアフラム21が形
成される。By this electrolytic etching, the n+ type buried layer 11 is etched to form a circular recess 19, and the portion of the n type epitaxial layer 12 facing this recess 19 becomes a circular strain-generating portion 20 (FIG. 1). A diaphragm 21 shown in is formed.
以上の製造方法により製造された半導体圧力センサは、
圧力Pが連通孔17、凹部19を介して導入され、これ
により起歪部20が歪んでゲージ13でこの歪みが電気
信号として検出される。The semiconductor pressure sensor manufactured by the above manufacturing method is
Pressure P is introduced through the communication hole 17 and the recess 19, thereby distorting the strain generating portion 20, and this distortion is detected by the gauge 13 as an electric signal.
なお、第1図(ホ)の電解エツチングの代りに超音波研
削加工などの機械加工を必要に応じて利用することもで
きる。In addition, instead of the electrolytic etching shown in FIG. 1(e), machining such as ultrasonic grinding may be used as needed.
〈発明の効果〉
以上、実施例と共に具体的に説明したように本発明によ
れば、凹部を形成するための円形のn+の埋込み層をp
形のシリコン基板の(−)極としての自己電極作用によ
り凹部の奥のn4の埋込み層まで等方性の電解エツチン
グで確実に除去するのでダイアフラムの起歪部の半径方
向の寸法精度が良く、また入手の困難なn+シリコン基
板を使う必要もなく、さらにウニ八単位でダイアフラム
加工を行うことができるので量産化加工が可能となるな
ど各種の効果がある。<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the circular n+ buried layer for forming the recess is
Due to the self-electrode action of the shaped silicon substrate as the (-) pole, the N4 buried layer deep inside the recess is reliably removed by isotropic electrolytic etching, resulting in good dimensional accuracy in the radial direction of the strain-generating part of the diaphragm. In addition, there is no need to use n+ silicon substrates, which are difficult to obtain, and the diaphragm can be processed in units of eight, making mass production possible.
第1図は本発明の1実施例の製造方法を示す工程図、第
2図は従来の製造方法で製造された半導体圧力センサの
構成を示す構成図である。
1.21・・・ダイアフラム、2.19・・・凹部、3
.20・・・起歪部、5.17・・・連通孔、8・・・
感圧素子、10・・・シリコン基板、11・・・埋込み
層、12・・・n形エピタキシャル層、13・・・ゲー
ジ、14.15・・・絶縁膜。
第2図゛
竿 !
(イ) オム嘴虻
(ロ)工じヌAシャルベ表
(ハ)リーン形1収
(ニ)1!λ′Y1エツチ〉フ1
(ホ)電解エーノチレ7゛
(へ)り゛イヤ7ラムFIG. 1 is a process diagram showing a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a configuration diagram showing the configuration of a semiconductor pressure sensor manufactured by a conventional manufacturing method. 1.21...diaphragm, 2.19...recess, 3
.. 20... Strain part, 5.17... Communication hole, 8...
Pressure sensitive element, 10... Silicon substrate, 11... Buried layer, 12... N-type epitaxial layer, 13... Gauge, 14.15... Insulating film. Figure 2: Rod! (a) Omu beak (b) A charvet surface (c) Lean type 1 collection (d) 1! λ'Y1 Etch〉F1 (E) Electrolytic Enochire 7゛(H) Ear 7 Ram
Claims (1)
れた高濃度のn形シリコンの埋込み層を片方の面に持つ
p形シリコン基板の前記埋込み層の上にエピタキシャル
成長をさせてn形エピタキシャル層を形成し、さらにこ
の上にp形のゲージを形成した後、異方性エッチングに
より前記埋込み層の深さまで前記p形シリコン基板の前
記埋め込み層に対応する部分に凹部を形成し、前記p形
シリコン基板と前記n形エピタキシャル層との間に逆バ
イアス電圧を印加した状態でエッチング液に対してn形
エピタキシャル層を正電位に保持して前記埋込み層を電
解エッチングして除去し前記起歪部を形成することを特
徴とする半導体圧力センサの製造方法。An n-type epitaxial layer is formed by epitaxial growth on the buried layer of a p-type silicon substrate, which has a buried layer of highly concentrated n-type silicon on one side, which is patterned in the shape of a strain-generating portion that is displaced by the measurement pressure. Then, after forming a p-type gauge on this, a recess is formed in a portion of the p-type silicon substrate corresponding to the buried layer to the depth of the buried layer by anisotropic etching, and the p-type silicon substrate and the n-type epitaxial layer while applying a reverse bias voltage between the n-type epitaxial layer and the etching solution, the n-type epitaxial layer is held at a positive potential with respect to the etching solution, and the buried layer is electrolytically etched and removed to form the strain-generating portion. A method of manufacturing a semiconductor pressure sensor, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32901887A JPH01170054A (en) | 1987-12-25 | 1987-12-25 | Manufacture of semiconductor pressure sensor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32901887A JPH01170054A (en) | 1987-12-25 | 1987-12-25 | Manufacture of semiconductor pressure sensor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01170054A true JPH01170054A (en) | 1989-07-05 |
Family
ID=18216678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32901887A Pending JPH01170054A (en) | 1987-12-25 | 1987-12-25 | Manufacture of semiconductor pressure sensor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01170054A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03104463U (en) * | 1990-02-16 | 1991-10-30 | ||
JPH04148568A (en) * | 1990-10-12 | 1992-05-21 | Toshiba Corp | Semiconductor pressure sensor and manufacture of the same |
JP2002243516A (en) * | 2001-02-13 | 2002-08-28 | Denso Corp | Method of manufacturing sensor having thin film part |
-
1987
- 1987-12-25 JP JP32901887A patent/JPH01170054A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03104463U (en) * | 1990-02-16 | 1991-10-30 | ||
JPH04148568A (en) * | 1990-10-12 | 1992-05-21 | Toshiba Corp | Semiconductor pressure sensor and manufacture of the same |
JP2002243516A (en) * | 2001-02-13 | 2002-08-28 | Denso Corp | Method of manufacturing sensor having thin film part |
JP4639487B2 (en) * | 2001-02-13 | 2011-02-23 | 株式会社デンソー | Manufacturing method of sensor having thin film portion |
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