JPS6356962A - Manufacture of semiconductor pressure transducer - Google Patents
Manufacture of semiconductor pressure transducerInfo
- Publication number
- JPS6356962A JPS6356962A JP20237886A JP20237886A JPS6356962A JP S6356962 A JPS6356962 A JP S6356962A JP 20237886 A JP20237886 A JP 20237886A JP 20237886 A JP20237886 A JP 20237886A JP S6356962 A JPS6356962 A JP S6356962A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- etching
- cathode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 6
- 238000000866 electrolytic etching Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 4
- 230000035945 sensitivity Effects 0.000 abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 3
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Landscapes
- Pressure Sensors (AREA)
Abstract
Description
本発明は、半導体板の中央部が周辺部に比して薄い板厚
のダイヤフラムとして形成され、その部分にひずみゲー
ジを備えてなる起工部を有する半導体圧力変換器の製造
方法に関する。The present invention relates to a method for manufacturing a semiconductor pressure transducer having a diaphragm having a thickness thinner in the central part of a semiconductor plate than in the peripheral part, and having a construction part provided with a strain gauge in that part.
半導体圧力変換器の圧力感度のばらつきが小さく、特性
のそろった起歪部を得るためには、均一な板厚を有する
ダイヤフラムを形成することが必要である。そのような
ダイヤフラムを形成する一つの方法として、第2図に示
すように不純物を高濃度に添加したN゛の多結晶シリコ
ン基板1の片面にP形の低不純物濃度層2をエピタキシ
ャル成長させ、さらにその上にN形の低不純物濃度層3
を成長させ、この層3に表面からの不純物拡散によりP
形のひずみゲージ4を形成したのち、この半導体板10
の基板1側の面の周辺部をマスクしてエツチング液5の
中に浸清し、直流電a6により基板1を正とし、陰電極
7を負とする数■の電圧を印加し、電解エツチングによ
りN′基板1とP1!I2との間の境界面8にてエツチ
ングを停止させ、マスクされない中央部に凹部9を形成
していた。
しかしながら、この方法によると半導体板肉のN基板1
と2層2との間のP−N接合部に欠陥が存在した場合、
基板1に印加した電圧がその欠陥部を通してPrB6に
も印加されることにより、PN接合面8で凹部形成を停
止させることができなかった。In order to obtain a strain generating part with uniform characteristics and small variations in pressure sensitivity of a semiconductor pressure transducer, it is necessary to form a diaphragm having a uniform plate thickness. One method for forming such a diaphragm is to epitaxially grow a P-type low impurity concentration layer 2 on one side of a N2 polycrystalline silicon substrate 1 doped with high impurities, as shown in FIG. On top of that, an N-type low impurity concentration layer 3
is grown, and P is added to this layer 3 by impurity diffusion from the surface.
After forming the shaped strain gauge 4, this semiconductor plate 10 is
The peripheral part of the surface on the side of the substrate 1 is masked and immersed in the etching solution 5, and a voltage of several square meters is applied, with the substrate 1 being positive with a DC current a6 and the negative electrode 7 being negative, and electrolytic etching is performed. N′ substrate 1 and P1! Etching was stopped at the interface 8 with I2, and a recess 9 was formed in the unmasked central portion. However, according to this method, N substrate 1 of the semiconductor board
If there is a defect in the P-N junction between and two layers 2,
Since the voltage applied to the substrate 1 was also applied to the PrB6 through the defective portion, the formation of the recess at the PN junction surface 8 could not be stopped.
本発明は、半導体板の一面からのエツチングによってダ
イヤフラムを形成する際、所定の面でエツチングを確実
に停止して起歪部の均一な板厚のダイヤフラムを形成し
、圧力感度のばらつきが小さく、特性のよく揃った半導
体圧力変換器を製造する方法を提供することを目的とす
る。According to the present invention, when a diaphragm is formed by etching from one side of a semiconductor board, the etching is reliably stopped at a predetermined surface to form a diaphragm with a uniform thickness of the strain-generating part, and the variation in pressure sensitivity is small. It is an object of the present invention to provide a method for manufacturing a semiconductor pressure transducer with well-matched characteristics.
本発明は、−面側にひずみゲージが形成される半導体板
の多面側に高不純物濃度の第−居、その内側に低不純物
ン、蓋度の第二層を設け、この半導体(反をエツチング
液に浸ン貞し、液中に浸Y貞され、第二層と電気的に接
続される電極を負、第一層を正とする電圧を印加して電
解エツチングを行い、第−Isの厚さを深さとする凹部
な形成するもので、陰極と等電位の第二層と第一層の間
の不純物濃度境界面においてエツチングが確実に停止さ
れ、上述の目的が達成される。
【発明の実施例]
以下、第2図と共通の部分に同一符号を付した第1図を
引用して本発明の一実施例について説明する。
(110)面に平行で有効なピエゾ抵抗効果が得られる
<lTo >結晶方間を含み、例えば10”/cc以上
のひ素あるいは10”/cc以上のアンチモンを含むN
°高濃度単結晶シリコン基板1の片面に、10”/cc
以下のほう素をドーピングしたP形像不純物濃度N2を
エピタキシャル法によって成長させ、さらにその上に1
0”/cc以上のりんをドーピングしたN形像不純物濃
度N3をエビクキシャル成長させ、この層にP形層から
なるひずみゲージ4を形成する。このひずみゲージと反
対側の基板1の面の周辺部に、図示しないが、例えば酸
化膜のような1色穿(膜の上にニフケル、クロム14〜
30%を含有する金のような耐食性金rA嘆により被覆
してマスクとする。このようなシリコン仮10を図のよ
うに弗酸と純水の混合比率1:9のエツチング液5中に
入れ、マスク被着面に対向して白金陰電極7を配置し、
基板1と陰電極7間に基板を正とする数■の直流電圧を
電源6により印加して電気化学的にエツチングし、凹部
9を形成するが、この際PJ!!2と陰電極7を図のよ
うに接続して等電位とする。このような構成で電解エツ
チングすることにより、基板1と2層2との間の境界面
80P−N接合に欠陥が存在しても、PIFJ2の電位
が陰電極7の電位となるようにしたため、凹部9が境界
面8に到達すれば、それ以上エツチングは進まず、エツ
チングが停止する。低不純物濃度のPFJ2は必ずしも
N形基板1と異なる導電形でなくても、その間の不純物
濃度境界面で工、・チングを停止させることができるが
、この境界面をP−N接合とすることにより電気的絶縁
効果が生じ、ひずみゲージ4の出力へ雑音が入るのを防
止することができる。
【発明の効果]
本発明によれば、不純物濃度差のある2層の外層に正、
エツチング液中の陰11極に負の電圧を印加し、かつ2
層の内層を陰電極と等電位にすることにより2層の境界
面で確実に電解エツチングを停止させることができるた
め、所定の厚さで均一な板厚を有するダイヤフラムを備
えた起歪部を形成でき、圧力感度のばらつきが小さく、
特性のよく揃った半導体圧力変換器の製造することがで
きる。In the present invention, a first layer with a high impurity concentration is provided on the multi-sided side of a semiconductor plate on which strain gauges are formed on the negative side, and a second layer with a low impurity concentration and a high density is provided inside the layer, and this semiconductor (back side) is etched. Electrolytic etching is performed by applying a negative voltage to the electrode electrically connected to the second layer and positive to the first layer. By forming a concave portion with a depth equal to the thickness, etching is reliably stopped at the impurity concentration interface between the second layer and the first layer, which are equipotential with the cathode, and the above-mentioned object is achieved. Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1, in which parts common to those in FIG. 2 are given the same reference numerals. N containing <lTo> crystal direction, for example, containing 10"/cc or more of arsenic or 10"/cc or more of antimony.
° On one side of the high concentration single crystal silicon substrate 1, 10”/cc
The following boron-doped P-type impurity concentration N2 is grown by epitaxial method, and then 1
An N-type image impurity concentration N3 doped with phosphorus of 0"/cc or more is evixically grown, and a strain gauge 4 made of a P-type layer is formed in this layer. A peripheral portion of the surface of the substrate 1 on the opposite side from this strain gauge is formed. Although not shown, for example, one-color perforation such as an oxide film (Nifkel, chromium 14~ on the film)
The mask is coated with a corrosion-resistant gold alloy such as gold containing 30% gold. As shown in the figure, such a temporary silicone 10 is placed in an etching solution 5 with a mixing ratio of hydrofluoric acid and pure water of 1:9, and a platinum negative electrode 7 is placed opposite the surface to which the mask is applied.
A DC voltage of several square meters, with the substrate being positive, is applied between the substrate 1 and the negative electrode 7 by the power supply 6 to perform electrochemical etching to form the recess 9. At this time, PJ! ! 2 and the negative electrode 7 are connected as shown in the figure to make them equipotential. By electrolytically etching with such a configuration, even if there is a defect in the interface 80P-N junction between the substrate 1 and the second layer 2, the potential of the PIFJ 2 becomes the potential of the negative electrode 7. When the recess 9 reaches the boundary surface 8, etching does not proceed any further and the etching stops. The PFJ 2 with a low impurity concentration does not necessarily have a different conductivity type from the N-type substrate 1, but it is possible to stop etching at the impurity concentration interface between them, but this interface can be made into a P-N junction. This produces an electrical insulation effect and can prevent noise from entering the output of the strain gauge 4. [Effects of the Invention] According to the present invention, positive and
A negative voltage is applied to the cathode 11 in the etching solution, and 2
By making the inner layer of the layer equipotential with the cathode, electrolytic etching can be reliably stopped at the interface between the two layers. can be formed, and there is little variation in pressure sensitivity.
A semiconductor pressure transducer with well-defined characteristics can be manufactured.
【図面の簡単な説明】
第1図は本発明の一実施例におけるエツチング装置の断
面図、第2図は従来のエツチング装置の断面図である。
1:N0シリコン基板、2:Pエピタキシャル層、3:
Nエピタキシャル層、4:ひずみゲージ、5;エツチン
グ液、7:陰電極、9:凹部、10;第1図
第2図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an etching apparatus according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional etching apparatus. 1: N0 silicon substrate, 2: P epitaxial layer, 3:
N epitaxial layer, 4: strain gauge, 5: etching solution, 7: negative electrode, 9: recess, 10; Fig. 1 Fig. 2
Claims (1)
するダイヤフラムを残して凹部が形成され、該ダイヤフ
ラムの一面にひずみゲージを備えてなる起歪部を有する
ものを製造するに際し、半導体板のひずみゲージが形成
される面と反対側に高不純物濃度の第一層、その内側に
低不純物濃度の第二層を設け、該半導体板をエッチング
液に浸漬し、該液中に浸漬され、第二層と電気的に接続
される電極を負、第一層を正とする電圧を印加して電解
エッチングを行い、第一層の厚さを深さとする凹部を形
成することを特徴とする半導体圧力変換器の製造方法。 2)特許請求の範囲第1項記載の方法において、第一層
がN形、第二層がP形であることを特徴とする半導体圧
力変換器の製造方法。[Claims] 1) A concave portion is formed in the center of the semiconductor board leaving a diaphragm having a thinner thickness than the peripheral portion, and a strain-generating portion is provided on one surface of the diaphragm with a strain gauge. When manufacturing a semiconductor board, a first layer with a high impurity concentration is provided on the side opposite to the side where the strain gauge is formed, and a second layer with a low impurity concentration is provided inside that layer, and the semiconductor board is immersed in an etching solution. Then, electrolytic etching is performed by applying a negative voltage to the electrode electrically connected to the second layer and positive to the first layer, and making the thickness of the first layer the same as the depth. A method of manufacturing a semiconductor pressure transducer, comprising forming a recess. 2) A method for manufacturing a semiconductor pressure transducer according to claim 1, characterized in that the first layer is of N type and the second layer is of P type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20237886A JPS6356962A (en) | 1986-08-28 | 1986-08-28 | Manufacture of semiconductor pressure transducer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20237886A JPS6356962A (en) | 1986-08-28 | 1986-08-28 | Manufacture of semiconductor pressure transducer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6356962A true JPS6356962A (en) | 1988-03-11 |
Family
ID=16456503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20237886A Pending JPS6356962A (en) | 1986-08-28 | 1986-08-28 | Manufacture of semiconductor pressure transducer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6356962A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000009440A1 (en) * | 1998-08-11 | 2000-02-24 | Infineon Technologies Ag | Micromechanical sensor and corresponding production method |
US6284670B1 (en) | 1997-07-23 | 2001-09-04 | Denso Corporation | Method of etching silicon wafer and silicon wafer |
US6974709B2 (en) | 2002-04-03 | 2005-12-13 | Robert Bosch Gmbh | Method and device for providing a semiconductor etching end point and for detecting the end point |
-
1986
- 1986-08-28 JP JP20237886A patent/JPS6356962A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6284670B1 (en) | 1997-07-23 | 2001-09-04 | Denso Corporation | Method of etching silicon wafer and silicon wafer |
WO2000009440A1 (en) * | 1998-08-11 | 2000-02-24 | Infineon Technologies Ag | Micromechanical sensor and corresponding production method |
US6389902B2 (en) | 1998-08-11 | 2002-05-21 | Infineon Technologies Ag | Micromechanical sensor and method for its production |
US6974709B2 (en) | 2002-04-03 | 2005-12-13 | Robert Bosch Gmbh | Method and device for providing a semiconductor etching end point and for detecting the end point |
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