JPS6261374A - Manufacture of silicon diaphragm - Google Patents

Manufacture of silicon diaphragm

Info

Publication number
JPS6261374A
JPS6261374A JP20236885A JP20236885A JPS6261374A JP S6261374 A JPS6261374 A JP S6261374A JP 20236885 A JP20236885 A JP 20236885A JP 20236885 A JP20236885 A JP 20236885A JP S6261374 A JPS6261374 A JP S6261374A
Authority
JP
Japan
Prior art keywords
diaphragm
type
layer
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20236885A
Other languages
Japanese (ja)
Inventor
Masaki Hirata
平田 雅規
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20236885A priority Critical patent/JPS6261374A/en
Publication of JPS6261374A publication Critical patent/JPS6261374A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/07Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Pressure Sensors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain a silicon diaphragm having a uniform thickness of a designed value by an electrochemical etching method by setting the impurity densities in each of the layers of P-N junction silicon substrate the same. CONSTITUTION:The boron density of a P-type silicon substrate 1 of a P-N junction wafer used for an integrated pressure sensor is set the same as phosphorus density of an N-type epitaxial layer 2. A piezo resistor 3 is formed by boron ion implanting or thermal diffusing, a P-type well 13 is formed on the thick periphery of the sensor, an N-channel MOS IC or bipolar IC is integrated to be used for processing a signal. When the substrate 1 is etched by an electrochemical etching method, a diaphragm is formed by automatically stopping when the etching arrives at the layer 2. Even if heating step is added, the movements of impurities in the respective layers cancel each other so that the thickness of the effective layer 2 does not alter.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコンダイアフラムの形成方法に関し、特に
電気化学法を用いるシリコンダイアフラムの形成方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming a silicon diaphragm, and more particularly to a method of forming a silicon diaphragm using an electrochemical method.

〔従来の技術〕[Conventional technology]

従来、シリコンダイアフラムの形成にはエツチング時間
制御法、高濃度ボロン層によるエツチング停止法、電気
化学エツチング法などが用いられていた。例えば電気化
学エツチング法ではPN接合基板のN型層に正極性電圧
を印加し、P型層のみをエツチングにより除去すること
により行われる(アイ・イー・イー・イー トランプク
シ、ンズオン エレクトロン デパイシズ(IEEE 
TRANS−ACTIONS ON ELECTRON
 DEVICES、VOL、ED−30,7fL7 。
Conventionally, methods such as an etching time control method, an etching stop method using a high concentration boron layer, and an electrochemical etching method have been used to form a silicon diaphragm. For example, in the electrochemical etching method, a positive voltage is applied to the N-type layer of a PN junction substrate, and only the P-type layer is removed by etching.
TRANS-ACTIONS ON ELECTRON
DEVICES, VOL, ED-30, 7fL7.

JULY 1983))。JULY 1983)).

第2図に電気化学エツチング法に用いられた圧力センサ
用のPN接合ウェー・−の構造断面を示す。
FIG. 2 shows a structural cross section of a PN junction wafer for a pressure sensor used in the electrochemical etching method.

図において、P型基板1は面方位(100)で比抵抗3
Ω・副、厚さ175μmである。N型層2は比抵抗23
Ω・α、厚さ28.3μmである。ピエゾ抵抗3はP型
でイオン注入や拡散技術により形成され、このピエゾ抵
抗3の直下のP型基板1の部分をエツチングにより薄膜
化することによシ行われる。
In the figure, the P-type substrate 1 has a specific resistance of 3 in plane orientation (100).
The thickness is 175 μm. N-type layer 2 has a specific resistance of 23
Ω·α, thickness 28.3 μm. The piezoresistor 3 is of P type and is formed by ion implantation or diffusion techniques, and is etched by thinning the portion of the P type substrate 1 directly under the piezoresistor 3 by etching.

第3図にこの方法に使用するエツチング装置の模式図を
示す。図において、石英ビー力4に工。
FIG. 3 shows a schematic diagram of the etching apparatus used in this method. In the figure, the quartz bead force is 4.

チング液5を満しζヒータ6で液5を加熱する。Fill with a quenching liquid 5 and heat the liquid 5 with a ζ heater 6.

エツチング液5はエチレンジアミンにピロカテコールと
水を加えたものである。シリコンウニ・・−のN型層7
0表面に金属膜8を蒸着し、この金属膜8を電極として
電源9の正電圧を接続する。この状態でシリコンウェノ
・−のP型基板10をエッチングしてダイアフラムを形
成するものである。他方の電極に用いる白金を極11は
電流計12を介して接地されている。なお、エツチング
液の液温は115℃で印加筒、圧は0,6vである。P
型基板10がエツチングされ、N型層7に達するとエツ
チングが自動的に停止して均一な膜厚を有するダイアフ
ラムが形成される。
Etching solution 5 is a mixture of ethylenediamine, pyrocatechol, and water. N-type layer 7 of silicon sea urchin...
A metal film 8 is deposited on the 0 surface, and a positive voltage of a power source 9 is connected using this metal film 8 as an electrode. In this state, the silicon wafer P-type substrate 10 is etched to form a diaphragm. The platinum electrode 11 used as the other electrode is grounded via an ammeter 12. The temperature of the etching solution was 115°C, the pressure was 0.6V. P
The mold substrate 10 is etched, and when the N-type layer 7 is reached, the etching is automatically stopped and a diaphragm having a uniform thickness is formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、ダイアフラム型シリコン圧力センサの感度は
ダイアフラム部分の膜厚の2乗に反比例する。従って感
度ばらつきの小さい圧力センサを製造するためには膜厚
を正確に制御しなくてはならない。電気化学エツチング
法によれは膜厚はエピタキシャル層の厚さのばらつき内
に制御できる。
Incidentally, the sensitivity of a diaphragm type silicon pressure sensor is inversely proportional to the square of the film thickness of the diaphragm portion. Therefore, in order to manufacture a pressure sensor with small sensitivity variations, the film thickness must be accurately controlled. By electrochemical etching, the film thickness can be controlled within the variation of the epitaxial layer thickness.

しかしながらエピタキシャル層の厚さはゾロセス工程中
の熱処理により不純物が移動して変化するという問題が
ある。例えばピエゾ抵抗はゾロン等のイオンを注入し、
熱拡散により形成するが、この熱処理中に不純物が再分
布する。不純物の分布は不純物濃度と温度とにより決ま
り、例えば温度が1140℃の時シリコン中でメロンの
拡散係数は2X10’Cμ杼〕でリンの拡散係数も2X
10’〔ルVn〕と同程度であるので、高濃度領域側か
ら低濃度領域側に不純物が移動する。第2図に示した例
の場合ではP型基板1の方がN型層2より高濃度である
のでゾロンがN型層2側に移動し、実質のエピタキシャ
ル層は薄くなる。従ってダイアフラムを電気化学法によ
りエツチングしたと趣、膜厚が設計値より薄くなる。ま
た、ピエゾ抵抗形成時以外にも熱工程が続けられる場合
がある。例えば集積化圧力センサでは信号処理回路がダ
イアフラム周辺部に形成され、nチャネルMO8集積回
路を集積化する場合はN型エピタキシャル層に深いP形
つェルを形成する必要があるが、この時1200℃程度
の高温が加えられるので不純物の移動によりエピタキシ
ャル層は薄くなる。
However, there is a problem in that the thickness of the epitaxial layer changes due to movement of impurities due to heat treatment during the Zorocess process. For example, piezoresistors are made by implanting ions such as zolon,
It is formed by thermal diffusion, and impurities are redistributed during this heat treatment. The distribution of impurities is determined by the impurity concentration and temperature. For example, when the temperature is 1140°C, the diffusion coefficient of melon in silicon is 2X10'Cμ, and the diffusion coefficient of phosphorus is also 2X.
10' [Vn], impurities move from the high concentration region side to the low concentration region side. In the example shown in FIG. 2, since the concentration of P-type substrate 1 is higher than that of N-type layer 2, zolon moves toward N-type layer 2, and the actual epitaxial layer becomes thinner. Therefore, if the diaphragm is etched by an electrochemical method, the film thickness will be thinner than the designed value. Further, the thermal process may be continued even when piezoresistors are being formed. For example, in an integrated pressure sensor, the signal processing circuit is formed around the diaphragm, and when integrating an n-channel MO8 integrated circuit, it is necessary to form a deep P-type well in the N-type epitaxial layer. Since a high temperature of about °C is applied, the epitaxial layer becomes thinner due to the movement of impurities.

本発明の目的はこの問題点を解決l〜たエピタキシャル
基板を用いてシリコンダイアフラムを形成する方法を提
供することにある。
An object of the present invention is to provide a method for forming a silicon diaphragm using an epitaxial substrate that solves these problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、電気化学法によってダイアフラムを形成する
工程において、PN接合シリコン基板の各層の不純物濃
度を同一としたシリコンダイアフラムの形成方法でおる
The present invention is a method of forming a silicon diaphragm in which the impurity concentration of each layer of a PN junction silicon substrate is made the same in the step of forming the diaphragm by an electrochemical method.

〔作用〕[Effect]

P型シリコン基板のゾロン濃度とN型エピタキシャル層
のリン濃度とを同一とすることにより、約1140℃の
温度で熱処理しても互いの不純物拡散が打消し合い実質
的エピタキシャル層の厚さが変ワラないシリコンダイア
フラムが得られる。
By making the zolon concentration of the P-type silicon substrate and the phosphorus concentration of the N-type epitaxial layer the same, even when heat-treated at a temperature of about 1140°C, the impurity diffusion cancels each other out, and the actual thickness of the epitaxial layer changes. A silicon diaphragm with no cracks can be obtained.

〔実施例〕〔Example〕

以下に第1図に示す実施例によりシリコンダイアフラム
の形成方法を示す。第1図は集積化圧力センサの構造断
面図である。本発明に用いるPNN接合ウニ・−のP型
基板1は面方位(ioo)で不純物濃度が例えばI X
 10 ’ ”cm−’とする。N型層2はエピタキシ
ャル層で不純物濃度をP型基板と同じく1×10cWI
  とする。ピエゾ抵抗3はゾロンのイオン注入や熱拡
散により形成される。該圧力センサの周辺厚肉部にはP
型ウェル13が形成され、nチャネルMO8ICや・t
イボーラICを集積化して信号処理に用いられるもので
ある。このPNN接合ウニノーは電気化学エツチング法
にて従来同様に処理してP型基板1をエツチングすると
、エツチングがN型層2に達したときに自動的にエツチ
ングが停止してダイアプラムが形成される。
A method of forming a silicon diaphragm will be described below using an example shown in FIG. FIG. 1 is a cross-sectional view of the structure of an integrated pressure sensor. The P-type substrate 1 of the PNN junction sea urchin used in the present invention has a plane orientation (IOO) and an impurity concentration of, for example, IX
10'``cm-''.The N-type layer 2 is an epitaxial layer and has an impurity concentration of 1×10cWI, which is the same as that of the P-type substrate.
shall be. The piezoresistor 3 is formed by ion implantation or thermal diffusion of zolon. The peripheral thick wall part of the pressure sensor has P.
A type well 13 is formed, and an n-channel MO8IC or t
It integrates Ibora IC and is used for signal processing. When this PNN junction is etched by an electrochemical etching method in the same manner as in the prior art and the P type substrate 1 is etched, when the etching reaches the N type layer 2, the etching is automatically stopped and a diaphragm is formed.

この様に本発明では電気化学法によりシリコンをエツチ
ングしてダイアフラムを形成すると熱工程を加えても各
層の不純物濃度が同一のため、不純物の移動が互いに打
消し合い、実効的なエピタキシャル層の厚さが変わらな
い。本発明は実施例に示した不純物濃度の場合に限定さ
れるものでになく他の不純物濃度でも得られることは1
゛うまでもない。
In this way, in the present invention, when a diaphragm is formed by etching silicon using an electrochemical method, the impurity concentration in each layer is the same even if a thermal process is applied, so the movement of impurities cancels each other out, and the effective thickness of the epitaxial layer is increased. It doesn't change. The present invention is not limited to the impurity concentrations shown in the examples, but can also be obtained with other impurity concentrations.
゛Of course.

〔発明の効果〕〔Effect of the invention〕

したがって、本発明によれば、電気化学エツチング法を
用いて設計値どうりの均一な膜厚全有するシリコンダイ
アフラムを得ることができる効果を有するものである。
Therefore, according to the present invention, it is possible to obtain a silicon diaphragm having a uniform thickness in accordance with the design value using the electrochemical etching method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すシリコン基板の構造断面
、第2図は従来のダイアプラム型圧力センサの構造断面
図、第3図はダイアフラムを形成する為のエツチング装
置でおる。 1・・・P型基板、2・・・N型層、3・・・ピエゾ抵
抗、4・・・石英ビー力、5・・・エツチング液、6・
−・ヒータ、7・・・N型層、8・・・金属膜、9・・
・電源、10・・P型基板、IJ・・・白金電極、12
・・・電流計、J3・・・P型ウェル。
FIG. 1 is a structural cross-sectional view of a silicon substrate showing an embodiment of the present invention, FIG. 2 is a structural cross-sectional view of a conventional diaphragm type pressure sensor, and FIG. 3 is an etching apparatus for forming a diaphragm. DESCRIPTION OF SYMBOLS 1... P type substrate, 2... N type layer, 3... Piezoresistance, 4... Quartz bead force, 5... Etching liquid, 6...
- Heater, 7 N-type layer, 8 Metal film, 9...
・Power supply, 10...P-type substrate, IJ...platinum electrode, 12
...Ammeter, J3...P-type well.

Claims (1)

【特許請求の範囲】[Claims] (1)電気化学エッチング法を用いてシリコンダイアフ
ラムを形成する工程において、PN接合シリコン基板の
各層の不純物濃度を同一としたことを特徴とするシリコ
ンダイアフラムの形成方法。
(1) A method for forming a silicon diaphragm, characterized in that the impurity concentration of each layer of a PN junction silicon substrate is made the same in the step of forming a silicon diaphragm using an electrochemical etching method.
JP20236885A 1985-09-11 1985-09-11 Manufacture of silicon diaphragm Pending JPS6261374A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20236885A JPS6261374A (en) 1985-09-11 1985-09-11 Manufacture of silicon diaphragm

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20236885A JPS6261374A (en) 1985-09-11 1985-09-11 Manufacture of silicon diaphragm

Publications (1)

Publication Number Publication Date
JPS6261374A true JPS6261374A (en) 1987-03-18

Family

ID=16456342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20236885A Pending JPS6261374A (en) 1985-09-11 1985-09-11 Manufacture of silicon diaphragm

Country Status (1)

Country Link
JP (1) JPS6261374A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01222489A (en) * 1988-03-01 1989-09-05 Fujitsu Ltd Manufacture of semiconductor device
US5225377A (en) * 1991-05-03 1993-07-06 Honeywell Inc. Method for micromachining semiconductor material
EP0588371A2 (en) * 1992-09-18 1994-03-23 Nippondenso Co., Ltd. Semiconductor dynamic sensor having a thin thickness structure and its production method
JPH0897439A (en) * 1994-09-14 1996-04-12 Delco Electron Corp One-chip accumulation sensor
US5949118A (en) * 1994-03-14 1999-09-07 Nippondenso Co., Ltd. Etching method for silicon substrates and semiconductor sensor
JP2001068686A (en) * 1999-07-13 2001-03-16 Robert Bosch Gmbh Formation of diaphragm
US6284670B1 (en) 1997-07-23 2001-09-04 Denso Corporation Method of etching silicon wafer and silicon wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878470A (en) * 1981-11-04 1983-05-12 Mitsubishi Electric Corp Detecting device for semiconductor pressure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878470A (en) * 1981-11-04 1983-05-12 Mitsubishi Electric Corp Detecting device for semiconductor pressure

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01222489A (en) * 1988-03-01 1989-09-05 Fujitsu Ltd Manufacture of semiconductor device
US5225377A (en) * 1991-05-03 1993-07-06 Honeywell Inc. Method for micromachining semiconductor material
EP0588371A2 (en) * 1992-09-18 1994-03-23 Nippondenso Co., Ltd. Semiconductor dynamic sensor having a thin thickness structure and its production method
EP0588371A3 (en) * 1992-09-18 1995-05-10 Nippon Denso Co Semiconductor dynamic sensor having a thin thickness structure and its production method.
US5643803A (en) * 1992-09-18 1997-07-01 Nippondenso Co., Ltd. Production method of a semiconductor dynamic sensor
US5949118A (en) * 1994-03-14 1999-09-07 Nippondenso Co., Ltd. Etching method for silicon substrates and semiconductor sensor
US6194236B1 (en) 1994-03-14 2001-02-27 Denso Corporation Electrochemical etching method for silicon substrate having PN junction
JPH0897439A (en) * 1994-09-14 1996-04-12 Delco Electron Corp One-chip accumulation sensor
US5719069A (en) * 1994-09-14 1998-02-17 Delco Electronics Corporation One-chip integrated sensor process
US6284670B1 (en) 1997-07-23 2001-09-04 Denso Corporation Method of etching silicon wafer and silicon wafer
JP2001068686A (en) * 1999-07-13 2001-03-16 Robert Bosch Gmbh Formation of diaphragm

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