JPS6032993B2 - Semiconductor stress sensor and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to stress sensors, and more particularly to semiconductor stress sensors based on the piezoresistive effect.

The use of piezoresistive effects in silicon as a transducer for stress sensors is well known and such stress sensors are widely used.

A p-type region is typically formed by diffusion within an n-type silicon layer so that the p-type region functions as a resistor separated by a pn junction. Usually this resistance is formed in a diaphragm structure into which the stress to be measured is applied. By electrically contacting this p-type region or resistor at two points and measuring the resistance change between those contact points due to the piezoresistive effect while the stress is being applied, the applied stress can be measured. The size of can be measured. In order to protect such surface-diffused p-type regions from contamination, etc., which function as resistors for measuring stress using the piezoresistive effect, i.e., piezoresistors, some protection is applied to these regions and their surroundings. Must be covered with a cover.

A layer of silicon dioxide is usually provided on the surface of the silicon to cover at least the piezoresistor and its surrounding area, and often the entire surface of the silicon. A silicon dioxide-silicon interface naturally occurs at the surface of the silicon.

In this case, the p-type impurity is diffused from the vicinity of the region where the impurity concentration is the highest, that is, the portion of the piezoresistor where the impurity concentration is highest. This is a characteristic of surface diffusion processes. Since silicon dioxide incorporates certain p-type impurities during its formation, the maximum impurity concentration occurring at the surface of the silicon can vary significantly from the initial maximum concentration. Therefore, the maximum impurity concentration in silicon and the total amount of impurities in silicon decrease after diffusion. The maximum impurity concentration value is closely related to the conversion performance of the stress sensor with respect to temperature, which is the change in resistance versus applied stress as a function of temperature over a temperature range, ie, the temperature coefficient of the piezoresistance. The total resistance of a piezoresistor at any given temperature is of course related to the total amount of impurities contained in the p-type region.
Therefore, the resistance value of the piezoresistor at a particular temperature and the resistance response of the piezoresistor over a temperature range undergoes a change that is large enough to allow for the formation of the protective silicon dioxide layer.

Since the effects due to the formation of such a silicon dioxide protective layer vary widely between sensors, especially when the sensors are manufactured in different lots, the properties of the resulting piezoresistors can vary significantly. differ. This creates the difficult problem of having to compensate for differences in the characteristics of the stress sensors in order to generate an output signal of the stress sensing device that accurately reflects the stress applied to the stress sensor. Differences in the characteristics of piezoresistors are not the only reason why measurements using stress sensors such as those described above are inaccurate.

The silicon dioxide itself and other materials present on the diaphragm, including the presence or absence of metal interconnect leads connected to and across the piezoresistors, affect the diaphragm's thermal response to changes in temperature and applied stress. and change the mechanical response. These changes in the diaphragm response introduce further errors in the determination of the external stress applied to the diaphragm, but such changes are combined with the temperature-dependent internal stresses that occur at the interface between the diaphragm and its covering material. , caused by thermal and mechanical hysteresis. The extent of their influence differs quite significantly for different stress sensors. This is due to the fact that two or more materials within the diaphragm have different coefficients of thermal expansion. Hysteresis is due to the sliding of two or more materials relative to each other as stress or temperature changes. Typical situations in which these harmful stresses are generated internally include forming a silicon nitride layer on top of the silicon dioxide or adding organic materials on top of the silicon dioxide to prevent the silicon dioxide from being contaminated by ions. This is the case when it is covered.

The use of such organic substances also causes the problem of hysteresis. It makes economic sense to attempt to eliminate hysteresis in relatively low cost stress sensors by minimizing the problem, rather than by focusing on compensating for the effects of hysteresis. The reason is that compensation requires storage to remember the history of the hysteresis source over past cycles of the hysteresis loop. This problem is complicated by the different hysteresis loops between different stress sensors. Therefore, adding even greater problems to the hysteresis problem must be strictly avoided. Internal stresses are also clearly undesirable since they change the temperature coefficient and make temperature compensation difficult. However, attempts are often made to use such other coating materials to prevent ionic contamination of the silicon dioxide coating layer. This is because such ionic contamination causes the properties of the piezoresistor to change significantly over time. {i
}Contaminants in silicon dioxide, such as mobile ions that can reach the interface between silicon dioxide and silicon, and fixed silicon dioxide contamination ions that can induce charges at the interface between rigid silicon dioxide and silicon IJ. The diffused resistor, which is to be protected against charge, is also made more or less economically unstable electrically by the silicon dioxide layer provided.

This instability over time occurs because the charge that appears at the interface between silicon dioxide and silicon is in the area that was initially intended to be an n-type silicon region and in the area that was initially intended to be a p-type silicon region. This is because the outer portion of the silicon layer is changed to p-type.

Therefore, the original p-type region expands and the resistance value intended for the diffused p-type region becomes lower. Furthermore, this phenomenon also occurs between adjacent regions of opposite conductivity types, increasing the area of the pn junction. Due to this added p-type region, the area of the p-type region and the junction area become larger, and the resistance value originally planned for the p-type region becomes lower. As the junction area increases, the leakage current of the junction increases, which lowers the resistance value. The charge generated at the interface between silicon dioxide and silicon in the above sensor structure causes the electrical properties of the sensor to change over time.

This is because the amount and location of these charges change, which changes the p-type region or piezoresistance formed inside the silicon layer. These interfacial charges vary significantly in amount over time, closely related to the environment in which the sensor is used and how the sensor is manufactured.
The mobile charge also changes location in the silicon dioxide over time depending on the voltage and temperature applied during use of the sensor.
A signal indicative of external stress generated by a piezoresistor in a semiconductor stress sensor is almost always applied to a signal processing circuit.

At least the output of the stress sensor, which is generated in response to applied stress, always changes with temperature for silicon viezoresistors. That is, all piezoresistors have a temperature coefficient as shown in FIG. Figure 1 shows T,,T2,T3
three absolute temperatures and two maximum impurity concentrations MC,,M
A graph showing the relationship between the amount of change ΔR in resistance value and stress S in C2 is shown. In this case, the total number of acceptor atoms Np is kept constant. In order for the stress sensing device to accurately measure the external stress applied to it, this temperature characteristic of the piezoresistor must always be compensated for by the signal processing circuit.

If the characteristics shown in Figure 1 are {i} uniform among different sensors, {ii} do not change over time, and (iii) are independent of the history of applied heat and stress, then the signal The signal processing circuit is configured to cancel the temperature dependence of the piezoresistor so that the output signal from the processing circuit always accurately represents the stress applied to the stress sensor. However, as mentioned above, when a silicon dioxide layer is formed on the surface of silicon containing surface-diffused piezoresistors, the piezoresistors become non-uniform and the thermal and mechanical responses of the piezoresistors are affected. It deteriorates and its characteristics become unstable over time.

In many cases, it is completely impractical to completely compensate for hysteresis, so if the temperature characteristics differ, the amount of compensation must be adjusted for each unit. Furthermore, the resistance value of the piezoresistor, which varies from sensor unit to sensor unit, must be compensated for in the same way. Such compensation requires time and expense. And if the temperature characteristics and resistance value change over time during use, the compensation must be adjusted accordingly, making these stress sensors unusable in many applications. The semiconductor layer in the semiconductor pressure sensor according to the invention includes a selected first region of a second conductivity type provided for detecting applied stress, and except for the selected region, the semiconductor layer is of a first conductivity type provided for detecting applied stress. Consists of shapes.

This semiconductor layer is partially within the diaphragm of the sensor;
To some extent it is included within the constraint part of the sensor. At least a portion of the first region is included within the diaphragm and has a second conductivity type due to the addition of the first impurity. The concentration of the first impurity is highest in a portion of the diaphragm in the first region that is spaced apart from the surface of the semiconductor layer.
The first region can also be provided in a constrained portion of the semiconductor layer. A second region of the first conductivity type can be provided in the space between the region of highest first impurity concentration and a surface portion of the semiconductor layer separated from that region within the diaphragm. The semiconductor layer can be an epitaxial layer provided on a semiconductor substrate.

This substrate is provided with a recess for providing a diaphragm and a restraining structure. A material with a coefficient of thermal expansion very close to that of the substrate, such as silicon or a glass with a low coefficient of thermal expansion, can be bonded to the substrate to form a support or transmission means for the stress sensor, or to provide a fixed reference pressure on one side of the diaphragm. can also be included. Such semiconductor stress sensors include implanting ions into a semiconductor layer to form a first region and then forming a second region in the semiconductor layer.

The second region should not reach the portion of the first region where the first impurity concentration is highest. It is convenient to form this second region also by ion implantation. By forming the second region such that a portion of the first region intersects with a portion of the surface of the semiconductor layer within the constrained portion, the second region can be brought into electrical contact with the first region. By providing the semiconductor layer as an epitaxial layer on the semiconductor substrate, the diaphragm and the restraining portion can be provided by etching the substrate.

Advantageously, the epitaxial layer is provided as a first layer with a relatively high resistance, and a second layer with a lower resistance is provided on top of the first layer. Hereinafter, the present invention will be explained in detail with reference to the drawings.

It has been found that the piezoresistance temperature coefficient of a junction-separated piezoresistor in silicon is closely related to the highest concentration of impurities used to form the piezoresistor in silicon.

On the other hand, the resistance value of a piezoresistor is closely related to the total number of impurity atoms present in the piezoresistor separated by a junction. For this reason, the temperature coefficient value and total resistance value of the piezoresistance can be controlled independently to some extent by independently changing the maximum concentration of added impurities and the total number of atoms. The relationship between the temperature coefficient of piezoresistance and the maximum impurity concentration is as shown in FIG. As mentioned above, when the impurity concentration at the interface between silicon dioxide and silicon is the highest, the expected maximum impurity concentration and the expected number of impurity atoms present are strongly influenced by the conditions at the interface. .

These conditions closely depend on how the sensor is manufactured, are not uniform between different stress units, and change over time. As mentioned above, if it is desired to accurately compensate for temperature and time, it becomes necessary to adjust the signal processing circuit that receives the output signal of the stress sensor. Therefore, it is highly desirable in the structural design of a stress sensor to remove the piezoresistor or its highest concentration region from the immediate vicinity of the silicon dioxide-silicon interface.

Of course, the piezoresistor must be formed within the diaphragm fairly close to the surface of the silicon to cause sufficient strain in response to external stresses applied to the diaphragm. What is required to overcome most of the difficulties described above is to significantly reduce the spacing between the silicon dioxide and silicon interfaces. The first thing you can do for this is to create a region of the opposite conductivity type to that of the piezoresistor.
It is formed by diffusion just above the piezoresistor to separate the piezoresistor from the interface. In other words, it is a pinch resistance situation. This diffusion is performed at least over the sensing portion of the piezoresistor, and further onto any resistor extraction lead portion. However, for any surface diffusion, maximum diffusion occurs on the surface where the diffusion occurs. That is, this surface diffusion method also has a major drawback since it produces a region with the highest impurity concentration. That is, the piezoresistive diffusion and the overlying capping diffusion result in the highest impurity concentration near the surface of the semiconductor where these diffusions occur. but,
The second step in controlling diffusion during the manufacture of stress sensors.
The diffusion of the impurities cannot be well controlled either to the depth from the surface where they are diffused or to the doping profile of the impurity used in the first diffusion to form the piezoresistive region.

The impurity concentration in the piezoresistive region is highest at the surface where the impurity is diffused, and below that surface the impurity concentration profile changes rapidly with depth, with a second layer aimed at covering the piezoresistive region. Small changes in the depth of diffusion significantly change the total number of impurity atoms in the piezoresistor and the maximum concentration of those atoms. The unavoidability of such variations due to poor depth control of diffusion means that the electrical properties between different stress sensors vary considerably. Therefore, the resistance values differ between pinch resistors made in one lot and pinch resistors made in another lot, and the values of widely separated pinch resistors made on the same chip also differ.
Typical pinch resistance is also highly voltage dependent.

This is because the impurity concentration of the region in silicon that functions as a resistor is relatively low. This low concentration occurs because locations of high impurity concentration in the first diffusion region are effectively canceled out by the second diffusion. Since the impurity concentration in the silicon pinch resistance region is thus low, a sufficient depletion layer with high voltage dependence is formed in the pinch resistance region.
Therefore, the resistance value of the pinch resistor effectively increases. In order to avoid the problems that occur in the manufacturing method that includes the step of performing a second diffusion on the piezoresistor diffusion as described above, impurities are diffused into the silicon layer to form the piezoresistor, and then an epitaxial layer is formed on top of the piezoresistor. can be grown. This allows the piezoresistor to be separated from the surface of the silicon structure in much the same way as forming a buried layer in the structure of a bipolar transistor. However, difficulties also arise because the impurity concentration of the diffused piezoresistor is highest at the surface where the diffusion takes place. To grow an epitaxial layer, one of the first steps usually required is to etch the surface of the silicon layer to promote good crystal growth on that surface. This etching has a sufficiently large varying effect on the maximum impurity concentration of the diffused piezoresistor at the surface on which it is grown.
The reason is that the etching depth cannot be accurately controlled. Because the etching depth changes in this way, the maximum impurity concentration of the resulting piezoresistor varies depending on the stress sensor unit, resulting in lack of reproducibility.
In addition, since the total number of remaining impurity atoms varies depending on the etching depth, it greatly influences the total resistance value of these piezoresistors. This is very similar to the inability to control the diffusion depth in the double diffusion method described above. Furthermore, in epitaxial growth methods, there is always some diffusion from the silicon layer into the epitaxial layer. Therefore, in order to obtain a stress sensor with uniform temperature coefficient and total resistance value of the piezoresistors, the doped region for the piezoresistors with the highest impurity concentration region must be located at a level sufficiently below the surface of the silicon layer. It is necessary to form the silicon layer in the silicon layer.

This is also necessary to ensure stable operation of the sensor unit during its lifetime. Such a process allows the formation of uniform, stable resistors in silicon separated by semiconductor junctions. That is, through this process, a uniform and stable piezoresistance can be formed in the diaphragm of the stress sensor. Ion implantation of piezoresistive impurities results in very good reproduction of the depth and location of the highest impurity concentration region in the doped region of the piezoresistor, as well as the total number of impurity atoms in the doped piezoresistor region. This is because, using conventional ion implantation equipment, the region of highest impurity concentration can be formed at a selected depth below the surface of the silicon layer with precise control within reasonable tolerances. By implanting piezoresistive impurity ions, the maximum impurity concentration and the total number of impurity atoms can be set relatively independently and relatively freely. As a result, the temperature coefficient of the piezoresistance and the total resistance, ie the volume resistivity of the doped piezoresistive region, can be determined relatively independently. Once the requirements for forming the highest impurity concentration region of the piezoresistor deep enough into the silicon layer to avoid problems in later steps are met, further fabrication of the stress sensor is required. There are two ways to do it.

The silicon layer may be 'i' coated near its surface with a protective substance or altered to further protect the piezoresistor, or {ii
} or further surface treatment of the silicon layer can be omitted. The skin case described above is possible if there are no severe sources of contamination during use of the sensor or if the surface of the silicone layer can be protected from contamination during use. The advantage of doing so is that the oxidation steps necessary to form the electrical contacts can be carried out without absorbing significant amounts of impurities contained in the piezoresistive regions. However, stress sensor units become contaminated during use in many applications.

Therefore, a surface treatment of the silicon layer is required to protect the piezoresistor from contamination. Some of the piezoresistor protection methods mentioned above, which have been found to be problematic when used with diffused piezoresistors, require that the highest impurity concentration region of the piezoresistor be formed sufficiently deep within the silicon layer. Because it can be used, it can be used with significantly fewer problems. For example, for some applications, a piezoresistive protective silicon dioxide layer can be formed on the surface of the silicon layer.

In this case, the problems occurring at the silicon dioxide/silicon interface are not as severe as described above. The reason for this is that in this case, the piezoresistive region is quite far from the boundary surface, so the formation of the silicon dioxide protective layer has relatively little effect on the maximum impurity concentration and the number of impurity atoms in the piezoresistor. This is because it becomes smaller. However, the measurement accuracy of the stress sensor is limited because the oxide on the surface of the silicon layer causes the mechanical response of the silicon layer to an applied external stress to be different than in the absence of the oxide layer. Furthermore, the conditions at the interface between silicon dioxide and silicon also affect the total number of impurity atoms to some extent, so the accuracy of piezoresistance is also limited to some extent. Other methods of protecting the highest impurity concentration region of the piezoresistive region formed deep within the silicon layer include {i) protecting a region of the opposite conductivity type from that of the piezoresistive region; to diffuse onto or into; or {ii}
This includes growing a pitaxial layer of the opposite conductivity type over the piezoresistor.

Temperature coefficient of piezoresistance or total resistance due to uncertainty in the depth of diffusion of the protective layer or the depth of etching to perform epitaxial growth or the uncertainty of outward diffusion during epitaxial growth The change in value is not very large. Piezoresistiveness is due to the fact that the highest impurity region is away from the semiconductor junction formed by the diffusion region and the piezoresistive region or by the epitaxial layer and the piezoresistive region. However, due to the inability to control the diffusion process and the epitaxial growth process, it is now possible to approach the highest impurity concentration region of the piezoresistor and cause some degree of interaction with the piezoresistor. This will limit the characteristics to some extent.

The extent of such constraints increases as the region of highest impurity concentration in the piezoresistor approaches the region that is more affected by either the diffusion process or the epitaxial growth process. The difficulty encountered in forming the highest impurity concentration region of the piezoresistor deep enough in the silicon layer and then protecting it with one of the protection measures described above is the uniformity and stability of the piezoresistor. gender is influenced to some extent.

This magnitude is sufficiently large that stress sensor units obtained using these methods exhibit unsatisfactory performance in some applications requiring sufficiently high accuracy and uniformity. The use of better controllable surface treatment methods to protect the piezoresistors initially formed by ion implantation into the silicon layer will result in stress sensor piezoresistors that can be used with satisfactory performance in these applications. necessary to obtain.

Such surface treatment can be accomplished by using an ion implantation process in a region of a conductivity type opposite to that of the doped piezoresistive region. Due to this second ion implantation step, the junction-separated resistance formed in the silicon layer is very uniform and stable and is an excellent piezoresistance. Also, this piezoresistor is not affected by voltage much. Ion implantation also allows for very precise control of the location of impurity atoms below the surface of the silicon layer.

To this end, the protective region formed just below the surface of the silicon layer should not approach any part of the piezoresistive region that has a sufficiently high impurity concentration, i.e., the region with the highest impurity concentration among the piezoresistors. Confined to a very narrow area, not particularly close to the area. Furthermore, by providing a sufficiently wide separation between the region of highest impurity concentration in the piezoresistor and the region of sufficiently high impurity concentration in the protected region, the second implanted region can be separated from the remaining doped region. The breakdown value of the pn junction or semiconductor junction separated from the piezoresistive region becomes very high.

Additionally, relatively low temperature cycling, which requires annealing of the silicon layer to repair silicon lattice defects in the region formed by ion implantation, can reduce both the doped piezoresistive region and the protection region. Internally, a relatively small redistribution of impurity atoms takes place. Even when the silicon layer is formed as an epitaxial layer on a semiconductor substrate, this low temperature cycling results in a relatively small redistribution of impurity atoms between the silicon layer and its substrate. A semiconductor stress sensor with ion-implanted piezoresistors is shown in FIG.

FIG. 2A is a top view of a portion of the stress sensor. In the structure shown in FIG. 2, a piezoresistor is formed inside the silicon layer 9 on top of the silicon layer 9. FIG. A portion of this silicon layer 9 is a portion above a portion functioning as a restraining portion that supports the diaphragm portion of the stress sensor. Another section 11 is above the diaphragm section, indicated by the dashed line 12, and represents approximately the boundary between the two sections of the stress sensor restraint and diaphragm. Two piezoresistors 13 and 14 are provided inside the silicon layer 9, each piezoresistor having a portion included in both the diaphragm layer portion 11 and the constraining layer portion 10. The silicon layer 9 except near the contact 15
The piezoresistors 13 and 14 are shown with broken lines because they do not protrude above the surface. The silicon layer 9 has piezoresistors 13 and 14
It is formed of n-type silicon except for the part where is formed. These piezoresistors are p-type silicon. Typically, two piezoresistors are always used at the stress sensing location of the diaphragm to provide a double-strength signal to the signal processing circuit and to provide temperature compensation of the resistance. Piezoresistor 13 detects radial stress in diaphragm layer portion 11 . This can be seen from the fact that most of the resistance of this piezoresistor 13 occurs in a narrow arm along a radius drawn from the center of the diaphragm. On the other hand, the piezoresistor 14 detects stress in the tangential direction of the diaphragm layer portion. FIG. 2B is a sectional view taken along line 2B-2B in FIG. 2A. The silicon layer 9 can be better understood from FIG. 2B.

A silicon layer 9 is indicated in this figure by braces and reference numeral 9. In the silicon layer 9, the junction between the constraint part and the diaphragm, that is, the part to the left of the boundary part 12 is
This is the restraining portion 10 in FIG. A, and the portion to the right of the boundary portion 12 is the diaphragm layer portion 11 in FIG. 2A. silicon layer 9
A broken line 16 is shown. This broken line 16 is used to approximately indicate the boundary between a portion 17 with a high impurity concentration and a portion 18 with a low impurity concentration in the silicon layer 9. The region 17 with high impurity concentration is provided in order to improve the result of the electrolytic etching performed to provide the recess in the substrate 19 on which the layer 9 is formed. This recess is formed on the right side of boundary 12 and forms the diaphragm part of the stress sensor. Piezoresistor 13 is shown with a broken line 20 drawn to approximately indicate the highest concentration region of impurities implanted to form it. Surface protection area 21
covers the piezoresistors 13 in the diaphragm layer portion 11 but does not cover all of the piezoresistors 13 in the constraining layer portion 10. The protected area 21 is formed by the diffusion method as described above.
It can be formed by an epitaxial growth method, an ion implantation method, or the like. Among these methods, if the protective layer 21 is formed by ion implantation, an accurate stress sensor unit with good reproducibility can be obtained. Electrical contact 15 is shown making ohmic contact to piezoresistor 13 via electrically insulating silicon dioxide ring 22 . As mentioned above, the silicon dioxide ring 22 can be provided with a certain thickness above the surface 23 of the silicon layer in order to protect the piezoresistor 13 from elements that contact the surface 23. of course,
Such a silicon dioxide coating limits the mechanical performance of the diaphragm, and the thinner the oxide layer, the less the limitation. If the oxide is very thin and other errors due to mechanical stress from mounting the substrate are relatively large, the effect of constraints is negligible. Refer now to FIG. This figure shows the result of the manufacturing steps carried out to obtain the structure shown in FIG. In the first process, the second
The piezoresistance region 13 shown in the figure is formed by ion implantation,
Region 21 is shown as an ion-implanted region in a subsequent step. Methods such as a diffusion method and an epitaxial growth method can also be used to form this region 21. After the formation of the piezoresistor by ion implantation, a silicon dioxide layer can be formed on the region 21 of the silicon layer surface 23 or on the portion of the piezoresistor 13 where the region 21 is not present. FIG. 3A shows the result of epitaxially growing an n-type layer 30 on a p+ substrate 31. FIG.

The resistivity of the substrate 31 is about 0.01 ohm. layer 3
0 is grown so that the resistivity of the first layer portion 32 is approximately 10 to 20 ohms and the resistivity of the second layer portion 33 is approximately 0.50 ohms. Layer portions 32 and 33 are approximately separated by a dashed line 34. Layer portions 32 and 33 are grown by conventional epitaxial growth techniques, with the impurity concentration during growth being increased during the final portion of the epitaxial growth. layer 3
0 is approximately 30 microns thick and layer portion 32 is approximately 20 microns thick. As mentioned above, the layer portion 33 aids in the subsequent etching step for the formation of the diaphragm portion. Layer portion 33 is a substantially equipotential layer to aid the electrolytic etching performed in this etching step. Also, the layer portion 33 lowers the injection efficiency of the semiconductor junction obtained from the formation of the piezoresistor, and since this layer portion has a high recombination rate, holes are transferred to the epitaxial layer during the etching process near the piezoresistor. Prevent from being etched inside. Thereafter, an oxide is grown on the exposed surface 35 of the epitaxial layer in a well known manner.

The results are shown in Figure 3B. In this step, silicon dioxide is matured to a thickness of approximately 12,000 angstroms to form masking layer 36. A silicon dioxide layer 36 is applied to form a piezoresistive region in the diaphragm layer portion and to form a piezoresistive lead to the constrained layer portion.
Conventional photoresist etching techniques are used to define the pattern in the wafer.

After this, an oxide layer 37 is grown over surface 35 to a thickness of approximately 600 angstroms. This oxide layer 37
functions as a scattering oxide. This scattering oxide acts as an amorphous coating over the regions selected for ion implantation, namely the piezoresistive region and the resistive lead extraction region, so that the implanted ions are exposed to the silicon inside layer 30. The ions are aligned in a lattice and scattered so that they do not penetrate deeper than expected given the average ion energy. The results of this step are shown in FIG. A deep ion implantation is then performed using boron ions with an average energy of about 300 KeV.

The ion beam is adjusted so that the amount of ions implanted at one time is 5.7×14 ions/day.

This results in a maximum boron concentration of about 1 and 9 atoms/mass and a surface sheet resistance of about 130 ohms/portion. The results of this step are shown in Figure 3D.

As can be seen from this figure, a p-type region 38 is formed in the layer portion 33 below the surface 35 of the silicon layer 30. A second dashed line 39 is shown to outline the location of the highest concentration of boron within this p-type region 38.
This location is typically 0.7 to 0.9 microns below surface 35, with the p-n junction defining the deepest part of p-type region 38 below surface 35 being approximately 1.3 microns below surface 35. be. Using these values, the final piezoresistor dimension from p-type region 38 is such that it has a resistance of approximately 5000 ohms.

This resistance value allows the sensor to be 'ii. Obtaining an output signal of sufficient magnitude for a given magnitude of stress applied to the diaphragm portion of the This satisfies two requirements: the current applied to excite the piezoresistor must be sufficiently small so that no errors occur. A piezoresistor having such a resistance value allows convenient dimensions of the surface 35 given the resistance value described above for the p-type region 38. The piezoresistors obtained in this way are not so long as to make it difficult to place them in the optimal position for stress measurements within the diaphragm.
It is also not so narrow that large resistance errors due to errors in cutting layer 36 to the required shape pose a problem. After the boron implant, the silicon dioxide mask 36 over the surface 35 of the silicon layer is removed using conventional photoresist etch techniques, except where it is desired to provide electrical contact to the piezoresistor.

Thus, as shown in FIG. 3E, a small portion of the scattering oxide layer 37 remains on the surface 35, protected from the photoresist layer portion 4. Of course, if a stress sensor with low accuracy and low stability is acceptable, a diffusion method or an epitaxial method can be used in the subsequent steps instead of the ion implantation method. The second ion implantation step is to irradiate the structure shown in FIG.
forming a shallow implanted region. This phosphorus ion implantation step is performed using phosphorus ions having an average energy of about 50 KeV and by irradiating a beam of 1 and 3 ions/ground. The highest phosphorus atom concentration that can be achieved is approximately 6.0×1 7 atoms/me. This highest concentration region ranges from surface 35 to approximately 0
．． It is formed at a position 1 micron below. The results are shown on the 3rd floor.
As shown in the figure. This figure shows the state when the photoresist mask is removed after the second ion implantation step. However, the scattering oxide layer 37 is still left in place to help find locations for electrical contacts that will be provided in later steps. An n-type region 41 is formed by this ion implantation. This region forms part of a pn junction separating the remaining p-type regions 38, 38' from the rest of silicon layer 30. Prior to dawn annealing, the implanted region was not deep enough to form a junction defining the upper region of region 38', but rather layer portion 3.
The impurity within 3 defines its boundaries. This portion of the p-n junction is located midway between region 38' and surface 35, approximately 0 from surface 35.
．． It is located 1 micron below. In this way, area 4
Since this p-n junction due to the formation of 1 is located well away from the highest boron concentration region 39 in the p-type region 38' after annealing, the small difference in the depth of this added p-n junction is The electrical and temperature characteristics of the p-type region 38' are hardly affected. Since this ion implantation process can be reliably controlled, changes in the depth of the added pn junction are very small. In addition, each area 41, 38
Since the maximum impurity concentrations of ' are significantly different from each other, the breakdown voltage of the pn junction between the two is a satisfactory value.

As an aid to this, the concentration of phosphorus in region 41 is low, i.e. sufficient to reconvert the surface of silicon layer 30 to n-type, and the depletion layer formed in region 41 during operation is The temperature should be sufficiently lower than the maximum boron temperature to the extent that surface 35 is not reached. The photoresist ion implant mask is removed followed by an anneal to repair damage to the silicon lattice caused by the ion implant. This is done by placing the moths in dry nitrogen for about one female at a temperature of 95,000°C, and then in moist oxygen instead of dry nitrogen for about 20 minutes. By using this moist oxygen, a silicon dioxide layer matures. This oxide layer is not allowed to grow on the surface 35 during this annealing since repair of lattice defects may be inhibited. Using moist oxygen, a silicon dioxide layer 42 approximately 2000 Angstroms thick is formed over surface 35 and scattering oxide layer 37. To minimize impurity redistribution in implanted regions 41 and 38', the annealing monoxide cycle is performed at a relatively low temperature of 95,000 °C.

The redistribution of impurities changes the structure of those regions and thus the structure of the stress sensor. This low temperature operation also prevents impurity redistribution between the n-type epitaxial layer 30 and the p+-type substrate 31. This is desirable during the diaphragm etching process to sharpen the etched green area. The results obtained by this step are shown in Figure 3G. The highest boron concentration range is approximately 0.7-0.
A thickness of 9 microns remains, with the highest phosphorus concentration region at surface 35.
or occur near it. Then areas 38' and 41
The junction between is approximately 0.2 microns below surface 35. However, it requires silicon dioxide thicker than the 2000 angstroms obtained with the competitive monoxide process.

By continuing the ripe growth in the oxidation step, there is a risk that impurity redistribution as described above will occur even if the operating temperature in this step is quite low. Therefore, by performing pyrolytic deposition of silicon dioxide at 30,000 Å until the silicon dioxide thickness is approximately 5,000 Å,
Further silicon dioxide is added. In FIG. 3G, for convenience of illustration, the silicon dioxide layer obtained in these two steps is shown included in layer 42. Holes 43 for electrical contacts are then provided in the silicon dioxide layer 42 using photoetching techniques.

The piezoresistor can be accessed through that hole. The results are shown in the figure on day 3. This hole 43 provides access to the p-type region 38'. Through this hole, ohmic electrical contact can be made to the p-type region 38'.

If this stress sensor unit is to be used in a corrosive atmosphere, it is necessary to create a special metallization structure using a combination of various metals to protect the sensor from the atmosphere. Unless it is used under extremely adverse conditions,
Conventional metallization techniques such as those used in conventional monolithic integrated circuits are used. In typical monolithic integrated circuits, aluminum is deposited to form the interconnect metallization network, and this stress sensor can also be used to make satisfactory electrical contacts using aluminum.
The results of this step are shown in FIG. Electrical contacts 44 are shown in this figure. After forming the metal contacts, portions of the silicon dioxide layer 42 are removed using conventional photoetching techniques except for those immediately adjacent to the contacts.

After this operation, the silicon dioxide layer is no longer present on the surface on which the applied stress is measured, so the silicon layer responds to the applied stress unhindered by such silicon dioxide. If the semiconductor mounting element has a significant amount of hysteresis or other tolerances in the stress sensor construction are large, a relatively thin silicon dioxide layer 42 can be left. The reason is that the errors caused by this layer and the sensor response are less important. A structure with unnecessary portions of layer 42 removed is shown in FIG. 3J. If this stress sensor is to be made in the form of a wafer and the outer part of the wafer is to be attached directly to a support, the thickness of the substrate 31 is chosen accordingly.

The part of the wafer that is fixed to the support serves as a constraint, and the remaining part functions as a diaphragm. However, in order to reduce the influence of hysteresis in the coupling means for coupling this stress sensor to its support mechanically, it is very common to provide part of the constraint in the semiconductor.

Since the substrate 31 is made very thick, a portion of it may be removed by etching or mechanical means, leaving the epitaxial layer, or the epitaxial layer and a portion of the substrate, as a diaphragm, and the remaining portion of the substrate and adhering to it. The epitaxial layer can be left as a constraint part. When etching this structure, the bottom of the substrate is covered with a metal such as platinum.

This platinum layer is provided with an opening for etching the substrate. Electrical contacts are made to the platinum, and then the entire structure is immersed in an electrolyte and electrolytically etched. The structure thus obtained is shown in FIG. 3K. This structure has a third
This corresponds to the structure shown in Figure 1. A support supporting the entire stress sensor is then mechanically bonded to the remainder of the substrate 31. The coefficient of thermal expansion of this support must approximately match that of the substrate 31 and the joint must be as hysteresis-free as possible. For example, a silicon support and gold bond can be used. Another typical structure bonded to substrate 31 is a glass tube with a low coefficient of thermal expansion.

This glass tube allows gas pressure to be measured by conveying gas from another point to the diaphragm section and measuring the stress that the gas exerts on the diaphragm. Another possibility for such a glass tube to be bonded to a stress sensor is to connect the glass tube to the sensor and to use a tube with a gas at a selected pressure or with a gas at a selected pressure at one end. This is to connect two pipes together. This stress sensor then becomes a differential pressure sensor based on zero pressure (absolute pressure) or some other pressure. Electrostatic bonding is one method of bonding the substrate 31 and low thermal expansion glass. The structure shown in Figures 2 and 3 is n
A type epitaxial layer is formed on a p-type substrate, and the formed piezoresistor is also p-type. but,
The parts can also be made of different conductivity types, as long as the piezoresistor and the surrounding semiconductor part are of different conductivity types. FIG. 4 is a graph showing the relationship between the impurity concentration C and the depth X from the surface of the silicon layer in the sensor manufactured as shown in FIG. The depth from the surface 35 is plotted in microns on the axis, and the impurity concentration is plotted on the vertical axis in m/m of a. Injected p-type impurity (boron)
The curve for the concentration of is denoted by Cp, and the remaining curve Cn
indicates the concentration of the n-type impurity (IJn) implanted in FIG. The impurity concentration after implantation is shown as a dashed line, and the curve of the final structure shown in FIG. 3 (after the dawn annealing step) is shown as a solid line.
A significant difference between the highest concentrations of n-type and p-type impurities in the final structure is evident from the position of the highest points of the two curves.

The intersection of the two solid curves approximately defines the final location of the pn junction, indicating that the junction is where a relatively low concentration of p-type impurities is present.

Thus, moving the point of intersection a little inward or outward from the position shown in Figure 4 has only a small effect on the number of impurity atoms in the p-type region;
It has little effect on the maximum concentration value of form impurities. Therefore, the resistance value and temperature coefficient of the piezoresistor are not significantly affected by this small movement of the intersection point. Since the maximum impurity concentrations of these two types of impurities are significantly different from each other, good junction breakdown voltage characteristics can be obtained. The value obtained is more than 10V. Brief Description of the Drawings Figure 1 is a graph showing the performance characteristics of a piezoresistor formed in a silicon layer with certain impurities, Figure 2 is a partial view of two parts of a semiconductor stress sensor, and Figure 3 is shown in Figure 2. FIG. 4 is a cross-sectional view showing the state of the stress sensor after each manufacturing process. FIG. 4 is a graph showing the outline of the impurity atom concentration of the stress sensor manufactured by the method shown in FIG.

9... Silicon layer, 13, 14... Piezoresistance, 21... Protection region, 30, 41... N-type layer,
31...substrate, 36,42...silicon dioxide layer, 37...scattering layer, 38,38'...p-type layer.

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Claims (1)

[Scope of Claims] 1. A semiconductor material stress sensor having a structural part substantially including a diaphragm and restraint means for restraining the peripheral edge of the diaphragm, the stress sensor comprising: a layer of semiconductor material that is of a first conductivity type except for selected regions, including a first selected region that acts as a piezoresistor; exhibiting a substantially second conductivity type by means of a first impurity having a region of maximum concentration within the first selected region and sufficiently distant from the first surface portion of the layer; The piezoresistor has a total resistance value and a temperature coefficient value at a selected temperature, and these total resistance values and temperature coefficient values are determined by the surface protection material,
being substantially unaffected by the presence of protective impurities or contaminants in areas of the layer at or adjacent to and sufficiently close to the first surface portion; Semiconductor stress sensor. 2. A method for manufacturing a semiconductor material stress sensor having a structural part substantially comprising a diaphragm and restraining means for restraining the peripheral edge of the diaphragm, the method comprising: first depositing a layer of semiconductor material of a first conductivity type; and using a first impurity in said layer through its first surface to form a first region of a second conductivity type, at least a portion of which acts as a piezoresistor. the first region is located in at least a portion of the layer that includes the diaphragm and that would be included in the first region that has a maximum concentration region of the first impurity; The region of maximum impurity concentration is sufficiently separated from the first surface portion of the layer to allow surface protection materials, protective impurities, or other materials that may adhere to the first surface portion and adjacent portions thereof. wherein said piezoresistor has both a total resistance value and a temperature coefficient value at a selected temperature that are substantially unaffected by the presence or absence of contaminants. A method for manufacturing a stress sensor.