JPS60211945A - Method for formation of thin film - Google Patents

Method for formation of thin film

Info

Publication number
JPS60211945A
JPS60211945A JP6849784A JP6849784A JPS60211945A JP S60211945 A JPS60211945 A JP S60211945A JP 6849784 A JP6849784 A JP 6849784A JP 6849784 A JP6849784 A JP 6849784A JP S60211945 A JPS60211945 A JP S60211945A
Authority
JP
Japan
Prior art keywords
conductive layer
type conductive
layer
oxide film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6849784A
Other languages
Japanese (ja)
Other versions
JPH0527246B2 (en
Inventor
Masaki Hirata
平田 雅規
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6849784A priority Critical patent/JPS60211945A/en
Publication of JPS60211945A publication Critical patent/JPS60211945A/en
Publication of JPH0527246B2 publication Critical patent/JPH0527246B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PURPOSE:To enable to control film thickness accurately by a method wherein the non-etching part of the double layer silicon substrate consisting of a P type conductive layer and an N type conductive layer is coated by a silicon oxide film, and while a DC positive voltage is being applied to one conductive layer, an etching is performed on the other conductive layer using an etchant consisting of hydrazine. CONSTITUTION:A double layer silicon substrate 12 is composed of a P type conductive layer 13 and an N type conductive layer 14. A silicon oxide film 15 is formed on the surface of said double layer silicon substrate by performing a thermal oxidization or a CVD method. As the silicon oxide film 15 is formed on both sides of the double layer silicon substrate 12, a part of the silicon oxide film located on the side of the N type conductive layer 14 is removed, and an electrode is connected to the N type conductive layer. The silicon oxide film on the side of the P type conductive layer 13, excluding the region where an etching is not performed, is removed. Hydrazine is filled up in a container 16 as an etchant 17, it is heated up using a heater 18, and when a DC voltage power source 20 is connected in such a manner that platinum is used as a cathode electrode 19 and the N type conductive layer 14 is used as an anode, the P type conductive layer 13 which is not coated by the silicon oxide film is etched. The etching is stopped when the P type conductive layer is removed and the N type conductive layer comes in contact with the etchant 17.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はシリコン基板の薄膜化に関し、特に電気化学線
刻法によりシリコン薄膜を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to thinning a silicon substrate, and particularly to a method of forming a silicon thin film by electrochemical line engraving.

(従来技術とその問題点) シリコン基板全線刻溶液により触刻し薄膜化する技術は
ダイアフラム型シリコン圧力センサや加速度センサやサ
ーモパイル赤外線センサの製造に使われている。例えば
ダイアフラム型シリコン圧力センサは第1図に示す様に
シリコン薄膜slに拡散抵抗2が形成された構造となっ
ている。拡散抵抗2はイオン注入や熱拡散等によりシリ
コン基板3と反対導電型の不純物を導入して形成される
(Prior art and its problems) The technology of engraving the entire silicon substrate with an engraving solution to form a thin film is used in the manufacture of diaphragm-type silicon pressure sensors, acceleration sensors, and thermopile infrared sensors. For example, a diaphragm type silicon pressure sensor has a structure in which a diffused resistor 2 is formed in a silicon thin film sl, as shown in FIG. The diffused resistor 2 is formed by introducing impurities of a conductivity type opposite to that of the silicon substrate 3 by ion implantation, thermal diffusion, or the like.

シリコン薄膜部1は被測定圧力が印加された時に大きく
変形し、大きな、ら力が発生する様に薄膜化されている
。応力の発生により拡散抵抗2の抵抗値が変化して圧力
が検出される。シリコン薄膜部1は放電加工や化学線刻
液によ層形成される。例えば水酸化カリウムKOHやエ
チレン・ジアミン・ピロカテコールFDPやヒドラジン
を用いればシリコンは異方性線刻され第1図に示す様な
傾斜部4が形成される。(ioo)面シリコンウェーハ
を用いれば傾斜部4は54.7°の角度を成す(111
)面となる。あるいは硝酸HNO,やフッ酸HF’((
−用いれば等方性線刻され傾斜部は垂直となる。第1図
に示すダイアフラム型シリコン圧力センサの圧力−電気
信号変換の出力は応力に比例するが、応力がシリコン薄
膜部1の厚さの2乗に反比例する為、小さな膜厚ばらつ
きでも大きな感度ばらつきを発生する。感度ばらつきを
低減する為には正確に膜厚全制御する必要がある。従来
、膜厚の制御は前側時間により行なわれていたがシリコ
ン基板自身に厚さばらつきがある為、正確な膜厚制御は
困難であった。この為、均一な感度含有するダイアフラ
ム型圧力センサ全安洒にかつ大波生産することは困難で
めった。
The silicon thin film portion 1 is thinned so that it deforms greatly when the pressure to be measured is applied, and generates a large force. The resistance value of the diffusion resistor 2 changes due to the generation of stress, and pressure is detected. The silicon thin film portion 1 is formed as a layer by electrical discharge machining or chemical etching. For example, if potassium hydroxide KOH, ethylene diamine pyrocatechol FDP, or hydrazine is used, silicon is anisotropically etched to form an inclined portion 4 as shown in FIG. If a (ioo) plane silicon wafer is used, the inclined portion 4 forms an angle of 54.7° (111
) surface. Or nitric acid HNO, or hydrofluoric acid HF' ((
- If used, the isotropic line will be carved and the slope will be vertical. The output of the pressure-to-electrical signal conversion of the diaphragm type silicon pressure sensor shown in Fig. 1 is proportional to the stress, but since the stress is inversely proportional to the square of the thickness of the silicon thin film portion 1, even a small film thickness variation causes a large sensitivity variation. occurs. In order to reduce sensitivity variations, it is necessary to accurately control the entire film thickness. Conventionally, the film thickness has been controlled by the front side time, but since the silicon substrate itself has thickness variations, accurate film thickness control has been difficult. For this reason, it is difficult and rare to produce a diaphragm type pressure sensor with uniform sensitivity, complete safety, and large waves.

膜厚全正確に制御する為に様々な方法が提案されている
が性能や生産性や価格の点で問題がある。
Various methods have been proposed to accurately control the total film thickness, but there are problems in terms of performance, productivity, and cost.

先ず高濃度ボロン層を用いる方法全第2図にボす。First, the method using a high concentration boron layer is shown in Figure 2.

シリコン基板3の表面に5 X 101gcm−”以上
の高濃度ボロン層5をエピタキシャル成長あるいは熱拡
散により数μmの厚さに形成する。更にその上に低濃度
エピタキシャル層6を成長させ拡散抵抗2を形成する。
A high concentration boron layer 5 of 5 x 101 gcm-'' or more is formed on the surface of a silicon substrate 3 to a thickness of several μm by epitaxial growth or thermal diffusion.Furthermore, a low concentration epitaxial layer 6 is grown on it to form a diffused resistor 2. do.

低濃度エピタキシャル層6を成長式せるのは高濃度ボロ
ン層5の不純物濃度が極度に高く、この中に中濃度(約
3 X 10”cm−” )の拡散抵抗2を形成するの
が不可能な為である。線刻液は前述したKOH,FDP
、ヒドラジンである。この方法の欠点は高濃度ボロン層
と低濃度エピタキシャル層より構成されるシリコン基板
の価格が高いことと、熱工程中に高濃度ボロン層5のボ
ロンが再分布し、拡散抵抗2と接触しない様、低濃度エ
ピタキシャル層6の厚さを充分厚くしなくてはならない
ことである。次にPN接合シリコン基板を電気化学線刻
し薄膜全形成する方法を第3図に示す。PM導′屯層7
とN型導電層8とから底る2層シリコン基板の・りlえ
ばN型導電層8の表面を保腹膜9で被覆するとともに電
極配線?施す。陰極電極10は白金P、である。線刻溶
液11中に2層シリコン基板及び陰極電極10會浸し線
刻する。線刻溶液はフッ酸HFでN型4′tjL層8に
約0,5vの正極性直流電圧を印加するとP型導゛也層
7が線刻される。Pffl導電層7がすべて除去される
と線刻が停止し、2層シリコン基板はN型導電層8のみ
が残る。この電気化学線刻法により、箪化膜あるいは金
属蒸着膜全マスク材としてダイアフラム型シリコン圧力
センサの薄膜を形成することが可能である。しかし線刻
溶液としてフy酸I(Fk用するので等方性線刻ちれ、
第1図及び第2図で示した傾斜部4は垂直となジ薄膜端
邪に応力が集中し破壊強度が弱い。
The reason why the low-concentration epitaxial layer 6 can be grown is that the impurity concentration of the high-concentration boron layer 5 is extremely high, and it is impossible to form a medium-concentration (approximately 3 x 10 cm) diffusion resistor 2 therein. That's why. The marking liquid is KOH and FDP mentioned above.
, hydrazine. The disadvantages of this method are that the cost of the silicon substrate consisting of a high concentration boron layer and a low concentration epitaxial layer is high, and that the boron in the high concentration boron layer 5 is redistributed during the thermal process and does not come into contact with the diffused resistor 2. , the thickness of the low concentration epitaxial layer 6 must be made sufficiently thick. Next, a method for forming the entire thin film by electrochemical engraving on the PN junction silicon substrate is shown in FIG. PM conductive layer 7
If a two-layer silicon substrate is formed from the N-type conductive layer 8 and the N-type conductive layer 8, the surface of the N-type conductive layer 8 will be covered with a peritoneal membrane 9 and electrode wiring. give The cathode electrode 10 is platinum P. A two-layer silicon substrate and a cathode electrode 10 are immersed in an engraving solution 11 for engraving. The marking solution is hydrofluoric acid HF, and when a positive DC voltage of about 0.5 V is applied to the N-type 4'tjL layer 8, the P-type conductive layer 7 is marked. When the Pffl conductive layer 7 is completely removed, the engraving stops and only the N-type conductive layer 8 remains on the two-layer silicon substrate. By this electrochemical line engraving method, it is possible to form a thin film of a diaphragm type silicon pressure sensor using a dielectric film or a metal evaporated film as a total mask material. However, since phylic acid I (Fk) is used as the engraving solution, the engraving is isotropic.
In the sloped portion 4 shown in FIGS. 1 and 2, stress is concentrated at the vertical edge of the thin film and the fracture strength is low.

(発明の目的) 本発明の目的は前記欠点全除去し正確に膜厚の制御でき
る薄膜形成の方法を提供することにある。
(Objective of the Invention) An object of the present invention is to provide a method of forming a thin film that can eliminate all of the above-mentioned defects and accurately control the film thickness.

(発明の構成) 本発明によればP型尋電J@とN型導電層とより成る2
層シリコン基板の非線刻部全シリコン酸化膜で覆い一方
の導F4.J’giに直か[正極性電圧を印刀口しなが
ら他方の導電層をヒドラジンからなる線刻溶液により線
刻することを特徴とする薄j換形成の方法が得られる。
(Structure of the Invention) According to the present invention, 2 consisting of a P-type conductive layer J@ and an N-type conductive layer
All non-lined areas of the silicon substrate are covered with a silicon oxide film and one conductor F4. A method for forming a thin J'gi is obtained, which is characterized in that the other conductive layer is marked with a marking solution made of hydrazine while applying a positive voltage directly to the J'gi.

(実施例) 次に本発明について実施例を示す図面全参照して祝用す
る。第4図は本発明の一実施例金示す線刻装置の構成図
である。特にダイアフラム型シリコン圧力センサの薄膜
形成法を示す。2)fiシリコン基板工2はP塁導電層
13とN型導電層14とから構成されている。Pm、導
電層13の厚さは、例えば、350μmで比抵抗は10
〜15Ω−鋸であり、N型導電層14の厚さは、例えば
、20μmで比抵抗は3〜5Ω−mである。この様な2
層シリコン基板はP型シリコン基板に燐Pあるいは砒累
Aa ′に熱拡散することにより得られるし、あるいは
エピタキシャル成長技術によりP型シリコン基板上にN
型シリコン層を核層して容易に形成できる。画側2層シ
リコン基板の表面に熱酸化あるいはCVD(Chemi
cal Vapour Deposition )法に
よジシリコン酸化膜15を形成する。シリコン酸化膜1
5は2層シリコン基板12の両面に形成するがN型4電
MH4側のシリコン酸化膜の一部全除去しN型導電層に
電極を接続する。P型導電層13側のシリコン酸化膜は
Pm導電層を線刻しない領域のみを残して他は除去する
。容器16(ハ)線刻溶液17としてヒドラジンを満た
しヒータ18により加熱し液温を約90℃とする。白金
Ptを陰極電極19としてN型導電層14が陽極となる
様に約3vの直流電圧源20i接続すると、P型厚電層
13のシリコン酸化膜に被覆されてない部分が線刻され
る。今P型導電層13の結晶面方位’r(100)面と
するとヒドラジンには異方性があるので傾斜部には(1
11)面が現われ54.7°の角度となる。シリコン酸
化膜に被覆されていない部分の開口がP型溝電層13の
厚さに比べ充分大きいと線刻はN型導電層14に達する
葦で進む。P型溝電層が除去されN型4電層が線刻密液
17と接触すると線刻が停止する。これは陽極酸化によ
ジN型4電層の底面に薄いシリコン酸化膜が形成される
為と考えられる。p21導電層13が線刻されるのは印
加電圧がPN接合に対して逆方向電圧となっているので
P型導電I藷には電流が流れず酸化現象が起こらない為
でろろう。
(Examples) Next, the present invention will be described with reference to all drawings showing examples. FIG. 4 is a block diagram of a line engraving device showing one embodiment of the present invention. In particular, a method for forming a thin film of a diaphragm type silicon pressure sensor is shown. 2) The fi silicon substrate 2 is composed of a P-base conductive layer 13 and an N-type conductive layer 14. Pm, the thickness of the conductive layer 13 is, for example, 350 μm and the specific resistance is 10
The thickness of the N-type conductive layer 14 is, for example, 20 μm and the specific resistance is 3 to 5 Ω-m. 2 like this
The layered silicon substrate can be obtained by thermally diffusing phosphorus P or arsenic Aa' onto a P-type silicon substrate, or by depositing N on a P-type silicon substrate by epitaxial growth techniques.
It can be easily formed using a mold silicon layer as a core layer. Thermal oxidation or CVD (Chemistry) is applied to the surface of the two-layer silicon substrate on the image side.
A disilicon oxide film 15 is formed by a cal vapor deposition method. Silicon oxide film 1
5 is formed on both sides of the two-layer silicon substrate 12, but a portion of the silicon oxide film on the N-type 4-electrode MH4 side is completely removed, and electrodes are connected to the N-type conductive layer. The silicon oxide film on the P-type conductive layer 13 side is removed except for the region where the Pm conductive layer is not etched. Container 16 (c) Filled with hydrazine as a marking solution 17 and heated by a heater 18 to bring the temperature of the solution to about 90°C. When a DC voltage source 20i of about 3 V is connected using platinum Pt as a cathode electrode 19 and the N-type conductive layer 14 as an anode, the portion of the P-type thick conductive layer 13 not covered with the silicon oxide film is carved. Now, if the crystal plane orientation of the P-type conductive layer 13 is 'r(100) plane, since hydrazine has anisotropy, the inclined part has (1
11) A plane appears with an angle of 54.7°. If the opening in the portion not covered by the silicon oxide film is sufficiently large compared to the thickness of the P-type trench conductive layer 13, the line engraving progresses gradually until it reaches the N-type conductive layer 14. When the P-type groove conductor layer is removed and the N-type quaternary conductor layer comes into contact with the engraving dense liquid 17, the engraving stops. This is considered to be because a thin silicon oxide film is formed on the bottom surface of the di-N type four-electrode layer by anodic oxidation. The reason why the P21 conductive layer 13 is marked is probably because the applied voltage is in the opposite direction to the PN junction, so no current flows through the P-type conductive layer and no oxidation phenomenon occurs.

印加電圧の大きさは2v以上で上限は接合破壊電圧まで
である。
The magnitude of the applied voltage is 2V or more, and the upper limit is up to the junction breakdown voltage.

第4図は本発明の概念會示す簡単な構成図でめシ、実除
には線刻浴液17が蒸発して成度が変化しない様還流装
置を用い、また線刻が均一に進行する様線刻溶液をスタ
ー2等で攪拌することが望ましい。また図には明示され
ていないが2層シリコン基板12は両面とも鏡面研屋嘔
れており、Nm。
FIG. 4 is a simple configuration diagram showing the concept of the present invention. During actual cutting, a reflux device is used to prevent the engraving bath liquid 17 from evaporating and changing its composition, and the engraving progresses uniformly. It is desirable to stir the pattern marking solution using a Star 2 or the like. Also, although not clearly shown in the figure, both sides of the two-layer silicon substrate 12 are mirror-polished, and the thickness is Nm.

導電層14の表面にはP型不純物が拡散され感圧抵抗が
形成されている。また電極接続部はN型高濃度不純物が
拡散されオーム性接触が成されてbる。
P-type impurities are diffused into the surface of the conductive layer 14 to form a pressure-sensitive resistor. Further, in the electrode connection portion, N-type high concentration impurity is diffused to form an ohmic contact.

上記説明は(100)面2層シリコン基板を例にとって
なされたが勿論面方位は(100)面に限定されるもの
ではなく他の面方位であっても良い。
Although the above description has been made using a (100) plane two-layer silicon substrate as an example, the plane orientation is of course not limited to the (100) plane, and other plane orientations may be used.

またP型溝電層及びN型導電層の厚さと比抵抗も上述の
値に限定されるものではない。更に印加電圧の極性につ
いても逆方向として説明したが、順方向極性で線刻する
ことも可能と考えられる。この場合P型導電層に電極を
接続しN型導電層會線刻することになる。但しN型4電
層もバイアスされ順方向電流が流れるので印加電圧の大
きさには制限がるり、Nm導電層が陽極酸化でれること
なく線刻されPM導電層のみが陽極酸化されるような値
となる。
Further, the thickness and specific resistance of the P-type conductive layer and the N-type conductive layer are not limited to the above-mentioned values. Furthermore, although the polarity of the applied voltage has been described as being in the opposite direction, it is also possible to perform line engraving with the polarity in the forward direction. In this case, an electrode is connected to the P-type conductive layer and an N-type conductive layer is marked. However, since the N-type four conductive layer is also biased and a forward current flows, there is a limit to the magnitude of the applied voltage, and the Nm conductive layer is etched without being anodized and only the PM conductive layer is anodized. value.

(発明の効果) 本発明の薄膜形成の方法を用いてダイアフラム型シリコ
ン圧力センサ全製造すれば薄膜部の厚さは線刻時間に関
係なくエピタキシャル層の厚さ精度あるいは拡散層の深
さ精度により決着りる。エピタキシャル層の厚さ及び拡
散層の深さは現在の集積回路技術で高精度にかつ均一に
制御することが可能で従来の線刻時間制両法では得られ
ない高精度、均一な薄膜が得られ、高精度なダイアフラ
ム型シリコン圧力センサを大量に安価に提供できる。
(Effects of the Invention) If all diaphragm silicon pressure sensors are manufactured using the thin film forming method of the present invention, the thickness of the thin film portion will depend on the thickness accuracy of the epitaxial layer or the depth accuracy of the diffusion layer, regardless of the marking time. Settled. The thickness of the epitaxial layer and the depth of the diffusion layer can be controlled with high precision and uniformity using current integrated circuit technology, making it possible to obtain highly precise and uniform thin films that cannot be obtained with conventional line marking and time-based methods. This makes it possible to provide high-precision diaphragm-type silicon pressure sensors in large quantities at low cost.

本発明の薄膜形成の方法はダイアフラム型シリコン圧力
センサだけに適用されるものではなく、シリコン加速度
センサやサーモパイル赤外線センサの薄膜形成に応用す
ることが可能である。更にセンサデバイスだけでなく他
の薄膜機能デバイスへの応用も可能である。
The thin film forming method of the present invention is not only applicable to diaphragm type silicon pressure sensors, but can also be applied to forming thin films of silicon acceleration sensors and thermopile infrared sensors. Furthermore, it can be applied not only to sensor devices but also to other thin film functional devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は通常のダイアフラム型シリコン圧力センサの構
造断面図である。第2図は高濃度ポロン層により膜厚制
御したダイアフラム型シリコン圧力センサの構造断面図
である。第3図は従来の電気化学線刻法の構成図である
。第4図は本発明の一実施例を示す薄膜形成法の構成図
である。 1・・シリコン薄膜部 2・・拡散抵抗3・・・シリコ
ン基板 、4・・傾斜部5・・高濃度ボロン層 6・低
濃度エピタキシャル層7・・・P型溝電層 8・・・N
型導電層9・・保護膜 10・偏極電極 11・・線刻溶液 12・2層シリコン基板13・・P
型溝電層 14・・・N型導電層15・・・シリコン酸
化膜16・・容 器17・・・線刻溶液 18・ヒータ
。 19・・・陰極電極 20・・・直流電圧源71図 第2図 第3図 9 8 r 10 第4図 0 \ 8
FIG. 1 is a structural sectional view of a conventional diaphragm type silicon pressure sensor. FIG. 2 is a structural cross-sectional view of a diaphragm type silicon pressure sensor whose film thickness is controlled by a highly concentrated poron layer. FIG. 3 is a block diagram of a conventional electrochemical line engraving method. FIG. 4 is a block diagram of a thin film forming method showing an embodiment of the present invention. 1...Silicon thin film part 2...Diffused resistor 3...Silicon substrate, 4...Slanted part 5...High concentration boron layer 6.Low concentration epitaxial layer 7...P type trench conductor layer 8...N
Mold conductive layer 9..protective film 10.polarized electrode 11..engraving solution 12.two-layer silicon substrate 13..P
Type conductive layer 14... N-type conductive layer 15... Silicon oxide film 16... Container 17... Engraving solution 18. Heater. 19... Cathode electrode 20... DC voltage source 71 Figure 2 Figure 3 Figure 9 8 r 10 Figure 4 0 \ 8

Claims (1)

【特許請求の範囲】[Claims] P型導電層とN型導電層とより成る2層シリコン基板の
非線刻部全シリコン酸化膜で覆い一方の導電層に直流正
極性電圧全印加しながら他方の導電層をヒドラジンから
なる線刻溶液によシ線刻することft、%徴とする薄膜
形成の方法。
All non-lined areas of a two-layer silicon substrate consisting of a P-type conductive layer and an N-type conductive layer are covered with a silicon oxide film, and while a full DC positive polarity voltage is applied to one conductive layer, the other conductive layer is etched with lines made of hydrazine. A method of forming a thin film by marking a line in a solution.
JP6849784A 1984-04-06 1984-04-06 Method for formation of thin film Granted JPS60211945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6849784A JPS60211945A (en) 1984-04-06 1984-04-06 Method for formation of thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6849784A JPS60211945A (en) 1984-04-06 1984-04-06 Method for formation of thin film

Publications (2)

Publication Number Publication Date
JPS60211945A true JPS60211945A (en) 1985-10-24
JPH0527246B2 JPH0527246B2 (en) 1993-04-20

Family

ID=13375388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6849784A Granted JPS60211945A (en) 1984-04-06 1984-04-06 Method for formation of thin film

Country Status (1)

Country Link
JP (1) JPS60211945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376440A (en) * 1986-09-19 1988-04-06 Nec Corp Etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376440A (en) * 1986-09-19 1988-04-06 Nec Corp Etching

Also Published As

Publication number Publication date
JPH0527246B2 (en) 1993-04-20

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