JPH0527246B2 - - Google Patents
Info
- Publication number
- JPH0527246B2 JPH0527246B2 JP6849784A JP6849784A JPH0527246B2 JP H0527246 B2 JPH0527246 B2 JP H0527246B2 JP 6849784 A JP6849784 A JP 6849784A JP 6849784 A JP6849784 A JP 6849784A JP H0527246 B2 JPH0527246 B2 JP H0527246B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- layer
- type conductive
- silicon
- engraving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 239000010703 silicon Substances 0.000 claims description 41
- 239000010409 thin film Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 21
- 239000010408 film Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 19
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- HEMINMLPKZELPP-UHFFFAOYSA-N Phosdiphen Chemical compound C=1C=C(Cl)C=C(Cl)C=1OP(=O)(OCC)OC1=CC=C(Cl)C=C1Cl HEMINMLPKZELPP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009760 electrical discharge machining Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Vapour Deposition (AREA)
- ing And Chemical Polishing (AREA)
- Pressure Sensors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はシリコン基板の薄膜化に関し、特に電
気化学触刻法によりシリコン薄膜を形成する方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to thinning a silicon substrate, and particularly to a method of forming a silicon thin film by electrochemical engraving.
（従来技術とその問題点）
シリコン基板を触刻溶液により触刻し薄膜化す
る技術はダイアフラム型シリコン圧力センサや加
速度センサやサーモパイル赤外線センサの製造に
使われている。例えばダイアフラム型シリコン圧
力センサは第１図に示す様にシリコン薄膜部１に
拡散抵抗２が形成された構造となつてる。拡散抵
抗２はイオン注入や熱拡散等によりシリコン基板
３と反対導電型の不純物を導入して形成される。
シリコン薄膜部１は被測定圧力が印加された時に
大きく変形し、大きな応力が発生する様に薄膜化
されている。応力の発生により拡散抵抗２の抵抗
値が変化して圧力が検出される。シリコン薄膜部
１は放電加工や化学触刻液により形成される。例
えば水酸化カリウムKOHやエチレン・ジアミ
ン・ピロカテコールEDPやヒドラジンを用いれ
ばシリコンは異方性触刻され第１図に示す傾斜部
４が形成される。（100）面シリコンウエーハを用
いれば傾斜部４は54.7°の角度を成す（111）面と
なる。あるいは硝酸HNO3やフツ酸HFを用いれ
ば等方性触刻され傾斜部は垂直となる。第１図に
示すダイアフラム型シリコン圧力センサの圧力−
電気信号返換の出力は応力に比例するが、応力が
シリコン薄膜部１の圧さの２乗に反比例する為、
小さな膜厚ばらつきでも大きな感度ばらつきを発
生する。感度ばらつかを低減する為には正確に膜
厚を制御する必要がある。従来、膜厚の制御は触
刻時間により行なわれていたがシリコン基板自身
に厚さばらつきがある為、正確な膜厚制御は困難
であつた。この為、均一な感度を有するダイアフ
ラム型圧力センサを安価にかつ大量生産すること
は困難であつた。(Prior art and its problems) The technique of engraving a silicon substrate with an engraving solution to form a thin film is used in the manufacture of diaphragm-type silicon pressure sensors, acceleration sensors, and thermopile infrared sensors. For example, a diaphragm type silicon pressure sensor has a structure in which a diffused resistor 2 is formed in a silicon thin film portion 1, as shown in FIG. The diffused resistor 2 is formed by introducing impurities of a conductivity type opposite to that of the silicon substrate 3 by ion implantation, thermal diffusion, or the like.
The silicon thin film portion 1 is thinned so that it deforms greatly when the pressure to be measured is applied, and generates a large stress. The resistance value of the diffusion resistor 2 changes due to the generation of stress, and pressure is detected. The silicon thin film portion 1 is formed by electrical discharge machining or chemical engraving. For example, if potassium hydroxide KOH, ethylene diamine pyrocatechol EDP, or hydrazine is used, silicon is anisotropically etched to form the inclined portion 4 shown in FIG. 1. If a (100) plane silicon wafer is used, the inclined portion 4 will be a (111) plane forming an angle of 54.7°. Alternatively, if nitric acid HNO 3 or hydrofluoric acid HF is used, isotropic engraving is performed and the slope becomes vertical. Pressure of the diaphragm type silicon pressure sensor shown in Fig. 1
The output of the electric signal return is proportional to the stress, but since the stress is inversely proportional to the square of the pressure of the silicon thin film part 1,
Even small variations in film thickness cause large variations in sensitivity. In order to reduce variations in sensitivity, it is necessary to accurately control the film thickness. Conventionally, the film thickness has been controlled by the imprinting time, but since the silicon substrate itself has variations in thickness, it has been difficult to accurately control the film thickness. For this reason, it has been difficult to mass-produce diaphragm pressure sensors with uniform sensitivity at low cost.
膜厚を正確に制御する為に様々な方法が提案さ
れているが性能や生産性や価格の点で問題があ
る。先ず高濃度ボロン層を用いる方法を第２図に
示す。シリコン基板３の表面に５×1019cm-3以上
の高濃度ボロン層５をエピタキシヤル成長あるい
は熱拡散により数μｍの厚さに形成する。更にそ
の上に低濃度エピタキシヤル層６を成長させ拡散
抵抗２を形成する。低濃度エピタキシシヤル層６
を成長させるのは高濃度ボロン層５の不純物濃度
が極度に高く、この中に中濃度（約３×1018cm
-3）の拡散抵抗２を形成するのが不可能な為であ
る。触刻液は前述したKOH、EDP、ヒドラジン
である。この方法の欠点は高濃度ボロン層と低濃
度エピタキシヤル層より構成されるシリコン基板
の価格が高いことと、熱工程中に高濃度ボロン層
５のボロンが再分布し、拡散抵抗２と接触しない
様、低濃度エピタキシヤル層６の厚さを充分厚く
しなくてはならないことである。次にPN接合シ
リコン基板を電気化学触刻し薄膜を形成する方法
を第３図に示す。Ｐ型導電層７とＮ型導電層８と
から成る２層シリコン基板の例えばＮ型導電層８
の表面を保護膜９で被覆するとともに電極配線を
施す。陰極電極１０は白金Ptである。触刻溶液
１１中に２層シリコン基板及び陰極電極１０を浸
して触刻する。触刻溶液はフツ酸HFでＮ型導電
層８に約0.5Vの正極性直流電圧を印加するとＰ
導電層７が触刻される。Ｐ型導電層７がすべて除
去されると触刻が停止し、２層シリコン基板はＮ
型導電層８のみが残る。この電気化学触刻法によ
り、窒化膜あるいは金属蒸着膜をマスク材として
ダイアフラム型シリコン圧力センサの薄膜を形成
することが可能である。しかし触刻溶液としてフ
ツ酸HFを用いるので等方性触刻され、第１図及
び第２図で示した傾斜部４は垂直となり薄膜端部
に応力が集中し破壊強度が弱い。 Various methods have been proposed to accurately control film thickness, but they have problems in terms of performance, productivity, and cost. First, a method using a high concentration boron layer is shown in FIG. A highly concentrated boron layer 5 of 5×10 19 cm -3 or more is formed on the surface of a silicon substrate 3 to a thickness of several μm by epitaxial growth or thermal diffusion. Further, a lightly doped epitaxial layer 6 is grown thereon to form a diffused resistor 2. Low concentration epitaxial layer 6
The impurity concentration of the high-concentration boron layer 5 is extremely high, and medium-concentration (approximately 3×10 18 cm
This is because it is impossible to form the diffused resistor 2 of -3 ). The engraving liquids are the aforementioned KOH, EDP, and hydrazine. The disadvantages of this method are that the cost of the silicon substrate, which is composed of a high concentration boron layer and a low concentration epitaxial layer, is high, and that the boron in the high concentration boron layer 5 is redistributed during the thermal process and does not come into contact with the diffused resistor 2. Therefore, the thickness of the low concentration epitaxial layer 6 must be made sufficiently thick. Next, FIG. 3 shows a method of electrochemically etching the PN junction silicon substrate to form a thin film. For example, an N-type conductive layer 8 of a two-layer silicon substrate consisting of a P-type conductive layer 7 and an N-type conductive layer 8
The surface is covered with a protective film 9 and electrode wiring is provided. The cathode electrode 10 is made of platinum (Pt). The two-layer silicon substrate and cathode electrode 10 are immersed in an engraving solution 11 and engraved. The engraving solution is hydrofluoric acid HF, and when a positive DC voltage of about 0.5 V is applied to the N-type conductive layer 8, P
The conductive layer 7 is engraved. When the P-type conductive layer 7 is completely removed, the engraving stops and the two-layer silicon substrate becomes N
Only the mold conductive layer 8 remains. By this electrochemical engraving method, it is possible to form a thin film of a diaphragm type silicon pressure sensor using a nitride film or a metal vapor deposited film as a mask material. However, since hydrofluoric acid HF is used as the engraving solution, the engraving is isotropic, and the inclined portions 4 shown in FIGS. 1 and 2 are vertical, stress is concentrated at the ends of the thin film, and the breaking strength is weak.
（発明の目的）
本発明の目的は前記欠点を除去し正確に薄膜の
制御できる薄膜形成の方法を提供することにあ
る。(Objective of the Invention) An object of the present invention is to provide a method for forming a thin film that eliminates the above-mentioned drawbacks and allows precise control of the thin film.
（発明の構成）
本発明によればＰ型導電層とＮ型導電層とより
成る２層シリコン基板の非触刻部をシリコン酸化
膜で覆い一方の導電層に直流正極性電圧を印加し
ながら他方の導電層をヒドラジンからなる触刻溶
液により触刻することを特徴とする薄膜形成の方
法が得られる。(Structure of the Invention) According to the present invention, while the non-etched portion of a two-layer silicon substrate consisting of a P-type conductive layer and an N-type conductive layer is covered with a silicon oxide film and a DC positive polarity voltage is applied to one of the conductive layers, A method for forming a thin film is obtained, characterized in that the other conductive layer is engraved with an engraved solution consisting of hydrazine.
（実施例）
次に本発明について実施例を示す図面を参照し
て説明する。第４図は本発明の一実施例を示す触
刻装置の構成図である。特にダイアフラム型シリ
コン圧力センサの薄膜形成法を示す。２層シリコ
ン基板１２はＰ型導電層１３とＮ型導電層１４と
から構成されている。Ｐ型導電層１３の厚さは、
例えば、350μｍで比抵抗は10〜15Ω−cmであり、
Ｎ型導電層１４の厚さは、例えば、20μｍで比抵
抗は３〜5Ω−cmである。この様な２層シリコン
基板はＰ型シリコン基板に燐Ｐあるいは砒素As
を熱拡散することにより得られるし、あるいはエ
ピタキシヤル成長技術によりＰ型シリコン基板上
Ｎ型シリコン層を積層して容易に形成できる。当
刻２層シリコン基板の表面の熱酸化あるいは
CVD（Chemical Vapeur Deposition）法により
シリコン酸化膜１５を形成する。シリコン酸化膜
１５は２層シリコン基板１２の両面に形成するが
Ｎ型導電層１４側のシリコン酸化膜の一部を除去
しＮ型導電層に電極を接続する。Ｐ型導電層１３
側のシリコン酸化膜はＰ型導電層を触刻しない領
域のみを残して他は除去する。容器１６に触刻溶
液１７としてヒドラジンを満たしたヒータ１８に
より加熱し液温を約90℃とする。白金Ptを陰極
電極１９としてＮ型導電層１４が陽極となる様に
約3Vの直流電圧源２０を接続すると、Ｐ型導電
層１３のシリコン酸化膜に被覆されてない部分が
触刻される。今Ｐ型導電層１３の結晶面方位を
（100）面とするとヒドラジンには異方性があるの
で傾斜部には（111）面が現われ54.7°の角度とな
る。シリコン酸化膜に被覆されていない部分の開
口がＰ型導電層１３の厚さに比べ充分大きいと触
刻はＮ型導電層１４に達するまで進む。Ｐ型導電
層が除去されＮ型導電層が触刻溶液１７と接触す
ると触刻が停止する。これは陽極酸化によりＮ型
導電層の表面に薄いシリコン酸化膜が形成される
為と考えられる。Ｐ型導電層１３が触刻されるの
は印加電圧がPN接合に対して逆方向電圧となつ
ているのでＰ型導電層には電流が流れず酸化現象
が起こらない為であろう。印加電圧の大きさは
2V以上で上限は接合破壊電圧までである。(Example) Next, the present invention will be described with reference to drawings showing examples. FIG. 4 is a block diagram of an engraving device showing an embodiment of the present invention. In particular, a method for forming a thin film of a diaphragm type silicon pressure sensor is shown. The two-layer silicon substrate 12 is composed of a P-type conductive layer 13 and an N-type conductive layer 14. The thickness of the P-type conductive layer 13 is
For example, at 350 μm, the resistivity is 10 to 15 Ω-cm,
The thickness of the N-type conductive layer 14 is, for example, 20 μm, and the specific resistance is 3 to 5 Ω-cm. Such a two-layer silicon substrate is a P-type silicon substrate with phosphorus P or arsenic As.
Alternatively, it can be easily formed by laminating an N-type silicon layer on a P-type silicon substrate using an epitaxial growth technique. Thermal oxidation or
A silicon oxide film 15 is formed by a CVD (Chemical Vapeur Deposition) method. The silicon oxide film 15 is formed on both sides of the two-layer silicon substrate 12, but a portion of the silicon oxide film on the N-type conductive layer 14 side is removed to connect an electrode to the N-type conductive layer. P-type conductive layer 13
The silicon oxide film on the side is removed except for the region where the P-type conductive layer is not etched. A container 16 is filled with hydrazine as an engraving solution 17 and heated by a heater 18 to bring the temperature of the solution to about 90°C. When a DC voltage source 20 of approximately 3 V is connected using platinum Pt as the cathode electrode 19 and the N-type conductive layer 14 as the anode, the portion of the P-type conductive layer 13 not covered with the silicon oxide film is etched. Now, if the crystal plane orientation of the P-type conductive layer 13 is the (100) plane, since hydrazine has anisotropy, a (111) plane appears in the inclined portion, resulting in an angle of 54.7°. If the opening in the portion not covered by the silicon oxide film is sufficiently large compared to the thickness of the P-type conductive layer 13, the engraving progresses until it reaches the N-type conductive layer 14. The engraving stops when the P-type conductive layer is removed and the N-type conductive layer comes into contact with the engraving solution 17. This is considered to be because a thin silicon oxide film is formed on the surface of the N-type conductive layer by anodic oxidation. The reason why the P-type conductive layer 13 is engraved is probably because the applied voltage is in the opposite direction to the PN junction, so no current flows through the P-type conductive layer and no oxidation phenomenon occurs. The magnitude of the applied voltage is
Above 2V, the upper limit is the junction breakdown voltage.
第４図は本発明の概念を示す簡単な構成図であ
り、実際には触刻溶液１７が蒸発して濃度が変化
しない様還流装置を用い、また触刻が均一に進行
する様触溶液をスターラ等で撹拌することが望ま
しい。また図には明示されていないが２層シリコ
ン基板１２は両面とも鏡面研摩されており、Ｎ型
導電層１４の表面にはＰ型不純物が拡散され感圧
抵抗が形成されている。また電極接続部はＮ型高
濃度不純物が拡散されオーム性接触が成されてい
る。 FIG. 4 is a simple configuration diagram showing the concept of the present invention. In reality, a reflux device is used to prevent the concentration of the engraving solution 17 from evaporating, and the engraving solution is heated so that the engraving progresses uniformly. It is desirable to stir with a stirrer or the like. Although not clearly shown in the figure, both surfaces of the two-layer silicon substrate 12 are mirror-polished, and a P-type impurity is diffused into the surface of the N-type conductive layer 14 to form a pressure-sensitive resistor. In addition, N-type high-concentration impurities are diffused in the electrode connection portions to establish ohmic contact.
上記説明は（100）面２層シリコン基板を例に
とつてなされたが勿論面方位は（100）面に限定
されるものではなく他の方位であつても良い。ま
たＰ型導電層及びＮ型導電層の厚さと比抵抗も上
述の値に限定されるものではない。更に印加電圧
の極性についても逆方向として説明したが、順方
向極性で触刻することも可能と考えられる。この
場合Ｐ型導電層に電極を接続しＮ型導電層を触刻
することになる。但しＮ型導電層もバイアスされ
順方向電流が流されるので印加電圧の大きさには
制限があり、Ｎ型導電層が陽極酸化されることな
く触刻されＰ型導電層のみが陽極酸化されるよう
な値となる。 Although the above description has been made using a (100) plane two-layer silicon substrate as an example, the plane orientation is of course not limited to the (100) plane, and may be other orientations. Further, the thickness and specific resistance of the P-type conductive layer and the N-type conductive layer are not limited to the above-mentioned values. Furthermore, although the polarity of the applied voltage has been explained as being in the opposite direction, it is also possible to perform marking with the polarity in the forward direction. In this case, an electrode is connected to the P-type conductive layer and the N-type conductive layer is engraved. However, since the N-type conductive layer is also biased and a forward current flows, there is a limit to the magnitude of the applied voltage, so the N-type conductive layer is etched without being anodized, and only the P-type conductive layer is anodized. The value is as follows.
（発明の効果）
本発明の薄膜形成の方法を用いてダイアフラム
型シリコン圧力センサを製造すれば薄膜部の厚さ
は触刻時間に関係なくエピタキシヤル層の厚さ精
度あるいは拡散層の深さ精度により決まる。エピ
タキシヤル層の厚さ及び拡散層の深さは現在の集
積回路技術で高精度にかつ均一に制御することが
可能で従来の触刻時間制御法では得られない高精
度、均一な薄膜が得られ、高精度なダイアフラム
型シリコン圧力センサを大量に安価に提供でき
る。(Effect of the invention) If a diaphragm type silicon pressure sensor is manufactured using the method of forming a thin film of the present invention, the thickness of the thin film portion will be the same as the thickness accuracy of the epitaxial layer or the depth accuracy of the diffusion layer, regardless of the imprinting time. Determined by The thickness of the epitaxial layer and the depth of the diffusion layer can be controlled with high precision and uniformity using current integrated circuit technology, making it possible to obtain highly precise and uniform thin films that cannot be obtained with conventional imprinting time control methods. This makes it possible to provide high-precision diaphragm-type silicon pressure sensors in large quantities at low cost.
本発明の薄膜形成の方法はダイアフラム型シリ
コン圧力センサだけに適用されるものではなく、
シリコン加速度センサやサーモパイル赤外線セン
サの薄膜形成に応用することが可能である。更に
センサデパイズだけでなく他の薄膜機能デバイス
への応用も可能である。 The thin film forming method of the present invention is not only applicable to diaphragm type silicon pressure sensors;
It can be applied to thin film formation for silicon acceleration sensors and thermopile infrared sensors. Furthermore, the present invention can be applied not only to sensor deposition but also to other thin film functional devices.
第１図は通常のダイアフラム型シリコン圧力セ
ンサの構造断面図である。第２図は高濃度ボロン
層により膜厚制御したダイアフラム型シリコン圧
力センサの構造断面図である。第３図は従来の電
気化学触刻法の構成図である。第４図は本発明の
一実施例を示す薄膜形成法の構成図である。
１……シリコン薄膜部、２……拡散抵抗、３…
…シリコン基板、４……傾斜部、５……高濃度ボ
ロン層、６……低濃度エピタキシヤル層、７……
Ｐ型導電層、８……Ｎ型導電層、９……保護膜、
１０……陰極電極、１１……触刻溶液、１２……
２層シリコン基板、１３……Ｐ型導電層、１４…
…Ｎ型導電層、１５……シリコン酸化膜、１６…
…容器、１７……触刻溶液、１８……ヒータ、１
９……陰極電極、２０……直流電圧源。
FIG. 1 is a structural sectional view of a conventional diaphragm type silicon pressure sensor. FIG. 2 is a structural cross-sectional view of a diaphragm type silicon pressure sensor whose thickness is controlled by a high concentration boron layer. FIG. 3 is a block diagram of a conventional electrochemical engraving method. FIG. 4 is a block diagram of a thin film forming method showing an embodiment of the present invention. 1...Silicon thin film part, 2...Diffusion resistance, 3...
...Silicon substrate, 4...Slope portion, 5...High concentration boron layer, 6...Low concentration epitaxial layer, 7...
P-type conductive layer, 8...N-type conductive layer, 9...protective film,
10... cathode electrode, 11... engraving solution, 12...
Two-layer silicon substrate, 13... P-type conductive layer, 14...
...N-type conductive layer, 15...Silicon oxide film, 16...
...container, 17... engraving solution, 18... heater, 1
9...Cathode electrode, 20...DC voltage source.
Claims (1)
コン基板の非触刻部をシリコン酸化膜で覆い一方
の導電層に直流正極性電圧を印加しながら他方の
導電層をヒドラジンからなる触刻溶液により触刻
することを特徴とする薄膜形成の方法。1. The non-etched part of a two-layer silicon substrate consisting of a P-type conductive layer and an N-type conductive layer is covered with a silicon oxide film, and while a DC positive voltage is applied to one conductive layer, the other conductive layer is touched with a hydrazine layer. A method for forming a thin film characterized by engraving with an engraving solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6849784A JPS60211945A (en) | 1984-04-06 | 1984-04-06 | Method for formation of thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6849784A JPS60211945A (en) | 1984-04-06 | 1984-04-06 | Method for formation of thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60211945A JPS60211945A (en) | 1985-10-24 |
| JPH0527246B2 true JPH0527246B2 (en) | 1993-04-20 |
Family
ID=13375388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6849784A Granted JPS60211945A (en) | 1984-04-06 | 1984-04-06 | Method for formation of thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60211945A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6376440A (en) * | 1986-09-19 | 1988-04-06 | Nec Corp | Etching |
-
1984
- 1984-04-06 JP JP6849784A patent/JPS60211945A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60211945A (en) | 1985-10-24 |
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