JPH02170448A - Support system for deciding circuit size - Google Patents

Abstract

PURPOSE:To enhance a processing speed by a method wherein, after individual logic blocks constituting an LSI as a design object, a wiring part between the logic blocks and a delay amount of an input/output wiring signal have been allocated on the basis of information on a specification, a circuit and a connection including information on a delay amount of a signal of the LSI, sizes between the individual blocks, the wiring part, an input/output wiring part and the like are decided. CONSTITUTION:An input processing part 1 inputs information on a specification, a circuit and a connection including circuit information including the following: a whole specification where a delay amount of a signal of an LSI as a design object is included; a block specification of individual blocks constituting the LSI; a wiring specification of a wiring part connecting the individual logic blocks and of an input/output wiring part; a circuit specification of individual transistor levels. This information is stored in a data base part 2. A delay allocation part 3 allocates the delay amount of the signal regarding the individual logic blocks, the wiring part connecting the logic blocks and the input/output wiring part so as to satisfy the whole specification on the basis of the information, on the specification, the circuit and the connection, which has been stored in the base part 2; its result is stored in the base part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit size determination support system, and more particularly to a circuit size determination support system for determining the dimensions of transistors, wiring, etc. in the automatic design of a target LSI.

[Conventional technology]

Conventionally, this type of circuit size determination support system inputs circuit connection information of the LSI to be designed as an expanded overall circuit diagram at the transistor level.
The dimensions of wiring, etc., have been determined using a circuit simulator or a simple approximation formula based on the information on the overall circuit diagram at the transistor level and the overall specifications.

The dimensions of these transistors and wiring affect the amount of signal delay of the entire LSI, so these dimensions are determined so as to satisfy the specifications for this amount of delay.

[Problem to be solved by the invention]

The conventional circuit size determination support system described above is configured to determine the dimensions of transistors, wiring, etc. based on the overall circuit diagram information developed at the transistor level and the overall specifications, so the processing speed for determining the dimensions is fast. This has the disadvantage that it is slow and becomes increasingly difficult to handle, especially as the circuit scale increases.

An object of the present invention is to provide a circuit size determination support system that improves processing speed and can cope with an increase in circuit scale.

[Means to solve the problem]

The circuit size determination support system of the present invention includes an overall specification that includes information on the amount of signal delay of an LSI to be designed, block specifications for each logic block that constitutes the LSI, and wiring that connects each of these logic blocks. and an input processing unit that inputs specifications, circuits, and connection information including wiring specifications for input/output wiring, and transistor-level circuit information in each logic block, and A delay amount allocation unit that allocates signal delay amounts for the blocks, wiring between these logical blocks, and input/output wiring, and a delay amount allocated by this delay amount allocation unit and the specifications and
an in-block size determination unit that determines transistor dimensions and wiring dimensions in each logic block based on the circuit/connection information; and a delay amount allocated by the delay amount allocation unit and the specification/circuit/connection information. It also has a wiring size determination section that determines the dimensions of the wiring between each logical block and the input/output wiring.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The input processing unit 1 processes the overall specifications including information on the amount of signal delay of the LSI to be designed, the block specifications of each logic block constituting this LSI, the wiring connecting these logic blocks, and the input/output wiring. Specifications, circuits, and connection information including wiring specifications and transistor-level circuit information in each logic block are input and stored in the database section 2.

Based on the specifications, circuits, and connection information stored in the database section 2, the delay amount allocation section 3 allocates signals to each logic block, the wiring between each logic block, and the input/output wiring so as to satisfy the overall specifications. A delay amount is assigned and the result is stored in the database section 2.

The intra-block size determining unit 4 determines transistor dimensions and wiring dimensions within each logic block based on the specifications, circuits, and connection information stored in the database unit 2 and the delay amount allocated by the delay amount allocation unit 3. The determination is made and the result is stored in the database section 2.

The wiring size determination unit 5 determines the dimensions of the wiring between each logical block and the input/output wiring based on the specifications, circuits, and connection information stored in the database unit 2 and the delay amount allocated by the delay amount allocation unit 3. is determined and the result is stored in the database section 2.

The conversational modification section 6 modifies the processing results of each section stored in the database section 2 so that they can be input and output in a conversational manner, and controls the conversational input/output.

The output processing section 7 outputs the processing results of each section stored in the database section 2, ie, circuit dimension information such as transistor dimensions and wiring dimensions, under the control of the interactive modification section 6.

In this way, first, the signal delay amount of each logic block, the wiring between each logic block, and the input/output wiring is assigned, and the dimensions of transistors, wiring, etc. in each logic block, and each logic are determined according to the assigned delay amount. By determining the wiring dimensions between blocks and the input/output wiring dimensions,
Since circuit dimensions can be determined within a narrow range, processing speed for determining circuit dimensions, etc. can be improved.

Further, no matter how large the LSI is, it can be processed by breaking it down into logic blocks of a predetermined size, so it can be handled even if the circuit scale becomes large.

〔Effect of the invention〕

As explained above, the present invention is based on the specifications, circuits, and connection information that includes information on the amount of signal delay of the LSI to be designed. After allocating the signal delay amount of the input/output wiring, the circuit dimensions within each logic block, the dimensions of the wiring between each logic block, and the dimensions of the input/output wiring are determined, so that the circuit dimensions can be reduced within a narrow range. can be determined, improving processing speed, and even large-scale LSIs can be broken down into logical blocks for processing, making it possible to cope with larger circuit scales. There is.

Line dimension determining section, 6... interactive correction section, 7... output processing section.

Claims (1)

[Claims] An overall specification that includes information on the amount of signal delay of the LSI to be designed, block specifications for each logic block that constitutes the LSI, wiring specifications for wiring and input/output wiring that connects each of these logic blocks, and the above-mentioned an input processing unit that inputs specifications, circuits, and connection information including transistor-level circuit information in each logic block; A delay amount allocation section that allocates signal delay amounts for input/output wiring, and transistor dimensions and wiring in each logic block based on the delay amount allocated by this delay amount allocation section and the specifications, circuits, and connection information. An intra-block dimension determination section that determines the dimensions, and the dimensions of the wiring between each logical block and the input/output wiring are determined based on the delay amount allocated by the delay amount allocation section and the specifications, circuits, and connection information. 1. A circuit dimension determination support system comprising: a wiring dimension determination section.