JPH11251441A - Method and device for reducing signal delay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for reducing signal delays for a circuit design for reducing signal delays in an integrated circuit, etc., by adding minimum reguired circuits. SOLUTION: A buffer inserting means 5 and the gate multiplexing means 6 list the possibilities of buffer insertion and gate multiplexing in a target circuit. A solution set calculation means 7 calculates solution sets for combination of buffer insertion and gate multiplexing (such as wiring capacity and signal delay). An optimal solution selecting means 8 finds a configuration that achieves signal delay reduction required by adding minimum circuits from the combinations of buffer insertion and gate multiplexing, based on the circuit set results and selects a modified optimal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for designing a circuit, and more particularly to a method and a method for reducing a signal delay of a circuit in a computer device, an integrated circuit, and other electronic devices using buffer insertion and gate multiplexing. Related to the device.

[0002]

2. Description of the Related Art Conventionally, as a signal delay reducing method and apparatus of this kind, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 6-334042, a signal transmission delay in an integrated circuit, a logic circuit or the like is reduced. It is used for design and the like.

As a principle of the signal delay reducing method and apparatus, a method of inserting a buffer where a buffer circuit is inserted in a circuit or a method of performing gate multiplexing where a gate is provided in parallel with a gate in a circuit is typical. It is a target.

FIG. 6 is a block diagram showing an example of a signal delay reducing apparatus in a conventional circuit design using a buffer inserting means and a gate multiplexing means for performing such buffer insertion and gate multiplexing. As shown in FIG.
The configuration of the signal delay reducing device shown in FIG.
01, signal delay constraint violation detecting means 102, buffer inserting means 103, gate multiplexing means, and 104 circuit information output means 105.

[0005] The circuit information input means 101 is a circuit for reducing a signal delay such as a logic circuit.
This is means for storing and inputting as processing handling information together with the accompanying layout and wiring, delay constraint information, and the like. The signal delay constraint violation detecting means 102 determines whether the circuit input as the target circuit information in the circuit information input means 101 is a signal delay constraint (request signal arrival time) which is a requirement of a signal delay time required between input and output, for example. This is a means for determining whether or not the above condition is satisfied. The buffer inserting unit 103 is a unit that inserts a buffer into a target circuit. The gate multiplexing means 104 is a means for performing gate multiplexing on gates in the circuit. Circuit information output means 105
Is means for outputting circuit information changed by the delay reduction processing.

Next, the operation of the signal delay reducing device shown in FIG. 6 will be described for a case where a logic circuit is a target circuit. The configuration of the target logic circuit, the arrangement and wiring configuration of the logic circuit,
Information such as a signal delay constraint (specification on the delay time of each part of the circuit) is input to the circuit information input means 101. Based on the circuit information input in the circuit information input means 101, the signal delay constraint violation detecting means 102 determines whether or not the target logic circuit satisfies the signal delay constraint. If the signal delay constraint is satisfied, the circuit information output means 105 outputs circuit information as an appropriate circuit that does not require a design change, and ends.

However, if the target logic circuit does not satisfy the signal delay constraint, the buffer insertion means 103 inserts a buffer, and then the gate multiplexing means 104 performs gate multiplexing to change the logic circuit. The changed circuit information of the target logic circuit is input again to the circuit information input means 101, and the signal delay constraint violation detecting means 102
It is determined whether the signal delay constraint is satisfied as described above.

Thus, the design change of the target circuit, which is performed in the order of buffer insertion in the buffer insertion circuit 103 and gate multiplexing in the gate multiplexing means 104, is repeatedly executed until the target logic circuit satisfies the signal delay constraint. I do.

[0009]

In the prior art,
Although buffer insertion and gate multiplexing are closely related to each other in terms of improving the signal delay of the circuit, the circuit adopts a configuration in which each process is performed independently in a predetermined order. However, there is a problem in that the reduction of the signal delay cannot often be sufficiently obtained as a whole.

That is, the result of the delay reduction greatly depends on the order of application of the buffer insertion process and the gate multiplexing process, and there is a problem that good results are not often obtained in the overall delay improvement effect.

There is also a problem that the resulting circuit becomes unnecessarily large.

Further, in the prior art, there is a problem that a large processing time is required because it is necessary to repeat the processing of buffer insertion and gate multiplexing.

(Object of the Invention) An object of the present invention is to provide a signal delay reducing method and apparatus for reducing a signal delay of a given circuit.

It is another object of the present invention to provide a signal delay reducing method and apparatus capable of minimizing the scale of a circuit added for reducing signal delay.

Another object of the present invention is to provide a signal delay reduction method and apparatus capable of reducing the processing time required for signal delay reduction processing.

[0016]

SUMMARY OF THE INVENTION A signal delay reducing method and apparatus according to the present invention perform buffer insertion and gate multiplexing at the same time, enumerate possible combinations of these, and select an optimum circuit from them. Make up. That is, means (7 in FIG. 1) for enumerating solutions obtained by simultaneously applying buffer insertion and gate multiplexing to the target circuit (5 and 6 in FIG. 1) and selecting an optimal solution from the obtained solutions And an optimal solution selecting means (8 in FIG. 1).

According to the signal delay reduction method of the present invention, a division point is set in a wiring path of a circuit, and a combination of buffer insertion, gate multiplexing and non-divisional circuit change at each division point is enumerated as a solution set. The method is characterized in that a signal delay in each of the solution sets is calculated and an optimum solution for the required signal delay is selected. Also, the enumeration of the solution set is:
All combinations are made non-redundant by repeating buffer insertion and gate multiplexing at each division point from the output of the circuit to the input.

The signal delay reducing apparatus of the present invention is a solution comprising a combination of a wiring path dividing means for setting a dividing point of a circuit wiring path and a circuit change by inserting a buffer at a dividing point, multiplexing gates and not dividing. A solution set generating means for enumerating sets and calculating a signal delay of each change circuit, and an optimum solution selecting means for selecting an optimum solution for the constraint of the signal delay from the generated solution sets. The solution set generation means includes: circuit constant calculation means for calculating circuit constants such as wiring capacitance and resistance of each part of the circuit; circuit change means for enumerating the solution sets (buffer insertion, gate multiplexing means); Calculating means for calculating a signal delay based on the circuit constants and the respective change circuits.

(Operation) By simultaneously applying the buffer insertion and the gate multiplexing to the target circuit, the signal delay reduction result does not depend on the application order of the buffer insertion and the gate multiplexing. Comprehensive judgment is made on the delay reduction result and the like, and an optimum circuit can be obtained.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to FIG. 1, the configuration and function of a signal delay reducing method and apparatus according to an embodiment of the present invention will be described.

The configuration for reducing the signal delay according to the present embodiment includes circuit information input means 1, signal delay constraint violation detecting means 2, wiring path dividing means 3, circuit constant calculating means 4, buffer inserting means 5, gate multiplexing. And a solution set calculation means 7, an optimum solution selection means 8, and a circuit information output means 9.

The operation of each section of the present embodiment will be described below.

The circuit information input means 1 performs a process of storing and inputting a circuit configuration relating to information of a target logic circuit and the like, layout and wiring information associated therewith, delay constraint information, etc. in order to reduce the delay by changing the circuit design. Do.

The signal delay constraint violation detecting means 2 determines whether or not the given circuit satisfies the given signal delay constraint based on the information inputted by the circuit information input means 1.

The wiring path dividing means 3 performs a process of searching for a wiring path of a target circuit as a candidate for buffer insertion and gate multiplexing and dividing the wiring path at the position.

The circuit constant calculating means 4 calculates circuit constants such as capacitance and resistance of the wiring leading to a candidate point for buffer insertion and gate multiplexing.

The buffer insertion means 5 enumerates combinations of buffer insertion at the division points (buffer insertion candidate points).

The gate multiplexing means 6 enumerates combinations of gate multiplexing at division points (gate multiplexing candidate points).

The solution set calculation means 7 includes a buffer insertion means 5
Based on each combination of buffer insertion and gate multiplexing obtained by the gate multiplexing means 6 and circuit constants such as wiring resistance and capacitance obtained by the circuit constant calculating means 4, buffer insertion at the division point Calculate the solution set for gate multiplexing.

The optimal solution selecting means 8 selects an optimal solution, which is information of a change circuit satisfying the signal delay constraint, from the solution sets obtained by the solution set calculating means 7.

The circuit information output means 9 outputs the circuit information such as the configuration of the logic circuit and the like and the layout and wiring changed by the delay reduction process together with the layout information of the inserted buffer and the multiplexed gate.

Next, the operation for reducing the signal delay of the present embodiment shown in FIG. 1 will be described.

It is assumed that a circuit to be subjected to signal delay reduction in the present invention has a tree structure having a source (input) gate as a root and a sink (output) as a leaf. Are used as terms defined in the field of graph theory.

The present invention divides a wiring path into a plurality of parts, and at each division point, a buffer insertion configuration of a subtree rooted at the division point and a non-redundant solution for all combinations of gate multiplexing at the division point. It is based on listing sets. Here, one solution is represented by a pair of a capacitance of a wiring portion directly connected without passing through a buffer and a request signal arrival time at a root corresponding to the capacitance.

In the enumeration of the solution set, repetition is repeatedly performed at each division point from the sink (output) to the source (input) of the circuit, so that the buffer insertion configuration and the source-gate multiplexing configuration of the entire circuit are obtained. Obtain nonredundant solution sets for all combinations. By selecting an optimal solution from the obtained solution set, a configuration relating to buffer insertion and gate multiplexing for the circuit is determined.

A specific example of the operation of the present embodiment will be described with reference to FIGS. Here, FIG.
FIG. 2 is a diagram illustrating a logic circuit as an example of a circuit on which signal delay is to be reduced, and an example of a wiring path and a division point thereof.
3 and 4 are diagrams showing a process of changing a circuit.
FIG. 4 is a diagram showing an example of a combination of these by buffer insertion and gate multiplexing. FIG. 5 is a diagram showing a modified circuit example that satisfies the finally obtained signal delay constraint.

First, the circuit information input means 1 stores and inputs the logic circuit shown in FIG. 2 as circuit information to be reduced in signal delay. The request signal arrival time and capacity are given to the input sink (output) of the circuit.

Next, the delay constraint violation detecting means 2 determines whether or not the input circuit satisfies the signal delay constraint (request signal arrival time). If the signal delay constraint is satisfied, the circuit information output means 9 outputs the circuit information and ends.

If the signal delay constraint is not satisfied, the wiring path dividing means 3 sets the dividing points I, J, K, L,
The wiring path is divided as indicated by M, N, and O. This division point is a candidate position for buffer insertion and gate multiplexing.

Next, the following processes 1) to 4) are recursively performed on the divided wiring paths from the sink of the circuit to the source at each division point obtained by the wiring path dividing means 3. By repeating, a non-redundant solution set is obtained for all combinations of buffer insertion and gate multiplexing of the entire circuit. 1) The circuit constant calculation means 4 calculates the wiring capacitance, resistance, etc. on the sink side (the wiring portion directly connected without passing through the buffer) from the target division point based on the solution set at the child division point (K, L). To calculate. For example, when the target division point is N as shown in FIGS. 3 and 4, calculation of the wiring capacitance and resistance of the partial path 17 is performed.

2) The buffer inserting means 5 enumerates combinations of the buffer insertion at the target division point and the solution sets at the child division points (K, L) (FIG. 3).

3) The gate multiplexing means 6 lists combinations of gate multiplexing at the target division point and solution sets at the child division points (K, L) (FIG. 4).

4) The known characteristics of the buffer and the gate, which are obtained by combining the case where the buffer is inserted, the case where the gate multiplexing is performed, and the case where neither is performed, at the target division point, , Resistance, etc.,
The solution set (capacity, request signal arrival time) calculating means 7 calculates the request signal arrival time at the target division point, and calculates a set of non-redundant solutions (capacity and request signal arrival time pairs).
The solution set obtained here is used in the calculation of the solution set at the parent division point (O) performed later.

The processing steps shown in FIGS. 3 and 4 are states in which the processing at the division points K and L has been completed and the division point N is to be processed. Here, a solution in which a buffer is inserted at each of the division points K and L is used as an example. However, in practice, a solution obtained by multiplexing gates at the division points K and L, a division point K,
In L, a solution without buffer insertion and gate multiplexing is also held. For example, FIG. 3 shows a solution obtained by inserting a buffer at the dividing points K, L, and N, and FIG. 4 shows a solution obtained by inserting a buffer at the dividing points K and L and multiplexing the gate at the dividing point N.

The above process is repeated until a solution set at the source of the circuit (a solution set for the entire circuit) is obtained.

When a set of solutions for the entire circuit is obtained,
The optimum solution selecting means 8 selects an optimum solution which satisfies the signal delay constraint by inserting a minimum necessary buffer and multiplexing gates from the obtained solutions, and the circuit output means 9
A buffer in which the information of the circuit corresponding to the optimum solution is inserted, and the position information of the multiplexed gate are output. For example, FIG.
Shows a specific example of a circuit in which the output optimal solution is changed. A buffer is inserted at the division points I and L, and gates are multiplexed at the division points M and N.

[0047]

According to the present invention, solutions can be enumerated while simultaneously considering the combination of buffer insertion and gate multiplexing, and the optimum solution can be selected from the solutions.

Therefore, the result of signal delay reduction does not depend on the order of application of buffer insertion and gate multiplexing.
Good results can be obtained globally with respect to the scale of the additional circuit and the result of delay reduction.

That is, the requirement for reducing the signal delay can be satisfied by the minimum necessary additional circuit.

Further, since it is possible to reduce unnecessary repetition of buffer insertion and gate multiplexing, it is possible to shorten a signal processing time.

[0051]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an application example of target circuit information and wiring path division.

FIG. 3 is a diagram illustrating an application example of buffer insertion.

FIG. 4 is a diagram illustrating an application example of gate multiplexing.

FIG. 5 is a diagram illustrating an example of an optimal solution of a circuit selected by an optimal solution selecting unit.

FIG. 6 is a block diagram of a signal delay reducing device in a conventional circuit design.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit information input means 2 Signal delay constraint violation detection means 3 Wiring path division means 4 Circuit constant calculation means 5 Gate multiplexing means 6 Buffer insertion means 7 Solution set (capacity, required signal arrival time) calculation means 8 Optimal solution selection means 9 Circuit information output means 10 Solution set generation means 11 Sink 12 Division point 13 Wiring path 14 Source gate 15 Source 16 Buffer insertion candidate 17 Partial path 18 Gate multiplexing candidate 19 Inserted buffer 20 Multiplexed gate

Claims (6)

[Claims] In a method for reducing a signal delay in a circuit design, a dividing point is set in a wiring route of a circuit, and a combination of a buffer insertion, a multiplexing of gates, and a circuit change by non-dividing at each dividing point is listed as a solution set. And calculating a signal delay in each of the solution sets and selecting an optimal solution for the required signal delay. 2. The method according to claim 1, wherein the enumeration of the solution set is performed in a non-redundant manner by repeatedly inserting a buffer and multiplexing gates at each division point from the output of the circuit to the input. Item 2. The signal delay reducing method according to Item 1. 3. A signal delay reducing device for circuit design, comprising a combination of a wiring path dividing means for setting a dividing point of a circuit wiring path and a circuit change by inserting a buffer at a dividing point, multiplexing gates, and not dividing. A solution set generating means for enumerating the solution sets and calculating a signal delay of each change circuit; and an optimum solution selecting means for selecting an optimum solution for the signal delay constraint from the generated solution sets. Delay reduction device. 4. The solution set generation means includes: circuit constant calculation means for calculating circuit constants such as wiring capacitance and resistance of each part of the circuit; and circuit change means for enumerating the solution sets (buffer insertion, gate multiplexing means). 4. The signal delay reducing device according to claim 3, further comprising: a calculating unit that calculates a signal delay based on the circuit constant and each of the change circuits. 5. The calculating means sequentially outputs information of each of the listed change circuits to the circuit constant calculating means, and inputs a circuit constant for calculating a signal delay of the circuit from the circuit constant calculating means. 5. The signal delay reducing device according to claim 4, wherein: 6. The method according to claim 1, wherein the enumeration of the solution set is performed in a non-redundant manner by repeatedly inserting a buffer and multiplexing gates at each division point from the output of the circuit to the input. Item 6. The signal delay reduction device according to item 4 or 5.