JPH0954787A - Circuit simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a simulation at a high speed by performing a circuit simulation for only an extracted partial circuit when the change of a circuit parameter is performed. SOLUTION: Circuit information on a net list, etc., is inputted in a circuit information holding part 4 from an external device by a circuit information input part 2 and the information is held. At this time, a partial circuit extraction part 6 extracts the circuit block affected by the change of a circuit parameter from the whole of the circuit in accordance with an extraction condition, a circuit simulation is performed for only the partial circuit extracted for the whole of the circuit in a simulation execution part 8, the simulation result is held in a simulation result holding part 5 and the result is outputted to an external device by a simultion result output part 9. Thus, simulation can be performed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulation device that performs a circuit simulation by using a computer to design an optimum circuit.

When designing a circuit, in order to obtain an optimum circuit, circuit simulation is performed while changing various parameters of circuit elements, and the influence thereof is analyzed. Alternatively, circuit simulation is performed when analyzing the characteristics when various loads are created in order to create a characteristic library of circuit elements.

[0003]

2. Description of the Related Art In a conventional circuit simulation device, when performing circuit simulation by changing various circuit parameters, the circuit simulation is performed for the entire circuit each time the circuit parameter is changed.

[0004]

Therefore, in the conventional circuit simulation apparatus, even if the parameters of some circuit elements are changed, the circuit simulation must be performed for the entire circuit every time the change is made. The simulation was time consuming and inefficient.

[0005]

SUMMARY OF THE INVENTION The present invention is a circuit simulation apparatus that includes a simulation execution unit and a circuit information holding unit that holds circuit information, and changes a circuit parameter in a circuit simulation device that performs a circuit simulation by a computer based on the circuit parameter. When there is a change, the partial circuit extracting unit that obtains a partial circuit affected by the change of the circuit parameter is provided, and when the circuit parameter is changed, the circuit simulation is performed only for the extracted partial circuit.

FIG. 1 shows the basic configuration of the present invention. In FIG. 1, reference numeral 1 is a circuit simulation device.

Reference numeral 2 denotes a circuit information input section for inputting circuit information such as a netlist and element information. 3 is a data holding unit.

A circuit information holding unit 4 holds a circuit. A simulation result holding unit 5 holds the simulation result.

Reference numeral 6 denotes a partial circuit extracting unit which extracts a circuit block whose change affects the circuit operation when the circuit parameter is changed. Reference numeral 8 denotes a simulation execution unit, which executes a circuit simulation.

Reference numeral 9 is a simulation result output unit.
The operation of the basic configuration of the present invention shown in FIG. 1 will be described. Circuit information such as a netlist and circuit element information is input from an external device by the circuit information input unit 2 and held in the circuit information holding unit 4. The simulation executing unit 8 performs a circuit simulation on the entire circuit. The simulation result is held in the simulation result holding unit 5, and is output from the simulation result output unit 9 to an external device.

When changing a circuit parameter, an extraction condition for extracting a circuit parameter to be changed from the circuit information input unit 2 and a circuit affected by the change of the circuit parameter (a depth as a reference for determining a circuit extraction (described later)) )
Etc.).

The partial circuit extraction unit 6 extracts a circuit block affected by the change of the circuit parameter from the entire circuit according to the extraction condition. The simulation execution unit 8 performs circuit simulation only on the extracted circuit. At that time, in the simulation of the entire circuit, the signal input from the unextracted circuit portion to the extraction circuit portion is treated as the signal input from the outside of the extraction circuit in the simulation of the extraction circuit.

The simulation result is held in the simulation result holding unit 5, and the simulation result output unit 9 is held.
Outputs the simulation result to an external device. A method of extracting a circuit having the basic configuration of the present invention shown in FIG. 1 will be described with reference to FIG.

FIG. 2A shows the entire circuit, which includes A, B, C,
D is a circuit block. n1, n2, n3, n4, n
5, n6 and n7 are nets, respectively. FIG. 2B is a diagram in which the circuit blocks affected by the operation are extracted when the parameters of the circuit elements of the circuit block A are changed.

Since the circuit block B and the circuit block D on the fan-out side of the circuit block A are affected, the circuit block A, the circuit block B, and the circuit block D are extracted. The input terminals of the extracted circuit are net n1,
n5. The input signal of the input terminal net n5 of the extraction circuit uses the signal obtained in the simulation of the entire circuit of FIG. 2 (a).

According to the present invention, when the circuit parameter is changed, the range affecting the changed circuit is extracted and the circuit simulation is performed, so that the simulation can be performed at high speed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows an embodiment of the system configuration of the circuit simulation apparatus of the present invention. In FIG. 3, 10 is a circuit simulation device.

Reference numeral 11 is a CPU. A storage unit 12 is a memory. Reference numeral 13 is a simulation execution unit.

Reference numeral 13 'is a simulation controller, which is a simulation executing unit 13 and a partial circuit extracting unit 14.
The execution control between the above is performed. Reference numeral 14 is a partial circuit extraction unit.

Reference numeral 15 is a circuit information holding unit. Reference numeral 16 is an extraction circuit holding unit. Reference numeral 17 is a simulation result holding unit.

An input / output control unit 18 controls the input / output of the input / output device. Reference numeral 31 is an interface with the input / output device. A magnetic disk device 32 holds circuit information and simulation results.

Reference numeral 33 is a display. Reference numeral 34 is a printer. Reference numeral 35 is a keyboard.

36 is a mouse. The operation of the system configuration of FIG. 3 will be described later. FIG. 4 is a functional block diagram of the partial circuit extraction processing of the present invention.

In FIG. 4, 14 is a partial circuit extracting section. 41 is a data holding unit for holding data such as circuit information.

Reference numeral 42 is a parameter change element list holding unit, which holds a list of elements whose parameters have been changed. Reference numeral 43 denotes a net list holding unit which holds a list of connection nets between circuit elements or circuit blocks.

Reference numeral 44 denotes a stack, which holds the circuit block obtained as a result of the path search.
Reference numeral 45 denotes a reference depth holding unit that holds a depth that serves as a reference for determination of extracting a circuit block (depth will be described later).

An extraction circuit block list holding unit 46 holds a list of the extracted circuit blocks. Reference numeral 51 denotes a path search unit, which searches a circuit net to obtain an adjacent circuit block or the like.

Reference numeral 52 denotes a depth determining unit which determines the depth from the reference circuit block based on the number of nets from the reference circuit block. Reference numeral 53 is a circuit block extraction unit, which is a process for obtaining a circuit block smaller than a predetermined depth.

Reference numeral 54 denotes an extraction circuit block output section,
This is a process of outputting the extracted circuit block to the simulation executing unit. Reference numeral 55 is a circuit information input unit for inputting a simulation target node, a network, a designated depth, and the like.

FIG. 5 shows an example of circuit connection. FIG. 5 (a) shows the entire circuit in circuit blocks. In FIG. 5 (a), A, B, C, D, E, F, G, H, I, J, K
Is a circuit block.

Each circuit block is connected by a net. FIG. 5 (b) is different from FIG. 5 (a) in the connection relationship. Only the circuit blocks A, B, C, D, E and F are shown. It differs from FIG. 5A in that the circuit block A and the circuit block E are connected.

The operation of the configuration of FIG. 4 will be described. Reference will be made to FIGS. 5 (a) and 5 (b) in the description of FIG. In FIG. 5A, it is assumed that the parameter of the circuit element of the circuit block C is changed, the circuit block C is used as the reference circuit block, and the reference value of the depth of the circuit block affected by the change of the circuit parameter is 1. To do.

According to the circuit extraction of the present invention, a path reaching each circuit block is extracted from a circuit block (reference circuit block) including an element for changing a circuit parameter, and the path extends from the fan-out block to the fan-in block. The number of times of passing through the inter-block connection path is examined, and the number of times is taken as the depth of the path of each circuit block from the reference circuit block. If there are multiple paths to a circuit block, the smallest one is selected. Next, the depth reference value is compared with the depth of the path of each circuit block, and a circuit block with a depth less than the reference value is selected.

In FIG. 4, the circuit information input unit 55 inputs the parameter change information, the node list, the netlist, and the reference value of the determination depth of the circuit block from the external device. Then, the parameter changing element list is the parameter changing element list holding unit 42, the netlist is the netlist holding unit 43, the reference value of the depth for determining the circuit block extraction is the reference depth holding unit 45, and the selected circuit block. Is stored in the extraction circuit block list storage unit 46.

The path search unit 51 receives the information of the element for which the parameter is changed from the parameter change element list holding unit 42, and based on the netlist, lists up the adjacent circuit blocks connected to the circuit block including the element, One of them is selected and passed to the depth determination unit 52.
The rest is held in the stack 44. For example, in FIG. 5, assuming that the circuit parameter of the circuit block C is changed, the circuit block C is set as the reference block. Then, the circuit block B and the circuit block E are selected as the adjacent circuit blocks. When the circuit block B is selected, the circuit block E is held in the stack 44. Depth determination unit 5
2 determines the depth of the received circuit block (circuit block B). If the circuit block B is a fan-out block with respect to the parent circuit block (circuit block C) that is the source of the selection of the circuit block (circuit block B), the depth of the parent circuit block (in this case Since the circuit block C is the reference circuit block, the depth is the same as 0). If the circuit block B is a fan-in block, the value obtained by adding 1 is defined as the depth. If the depth is less than the reference value, the circuit block is extracted.
In this case, the reference value is 1 and the depth of the circuit block B is 1.
Therefore, the circuit block B is extracted.

Next, the path search unit 51 similarly finds the adjacent circuit block (circuit block A) of the circuit block (circuit block B) that has just been processed. When there are a plurality of adjacent circuit blocks, one of them is selected and the rest is held in the stack 44. In this case, since the adjacent circuit block is only the circuit block A, the circuit block A is selected (the circuit block C is already processed and is not extracted as the adjacent circuit block in this case). There are no circuit blocks to pass to the stack 44. Then, the selected circuit block (circuit block A) is passed to the depth determination unit 52. Depth determination unit 52
Determines the depth of the circuit block (circuit block A) passed as a parent of the circuit block (in this case, circuit block B) that is the source of the determination of the adjacent circuit block. In this case, the depth of the circuit block B is 1, and the depth of the fan-in block of the circuit block A is 2 in the circuit block A. Since the depth of the circuit block A exceeds the reference value, the circuit block A is not extracted. If the depth of the selected circuit block is less than the reference value, the circuit block is extracted.

Since the block A was not extracted, the process after the path search for the block A is not performed. Therefore, the path search unit 51 takes out the circuit block (circuit block E) held in the stack 44 and passes it to the depth determination unit 52. In this case, since the extracted circuit block is the circuit block E, the depth determination unit 52 determines the depth of the circuit block E. Since the circuit block E has not undergone the depth determination, the depth determination unit 52 determines the depth of the circuit block E using the circuit block C as a parent circuit block (when there are a plurality of paths including the circuit block E). Is (Fig. 5
(See (b)), the circuit block E may be selected multiple times). Since the depth of the parent circuit block C is 0 and the circuit block E is a fan-in block of the circuit block C, the depth is 1. The depth determination unit 52 determines the depth of the circuit block E, and the path to the circuit block E is the one that has been searched for the first time, and since the depth is also the reference value or less, it is extracted as the extraction circuit block. If the depth of the circuit block has been obtained once before, the old depth and the newly obtained depth are judged, and if the new depth is smaller, the depth is determined as the depth of the circuit block. Compare the depth and depth with the reference value. If the old depth is smaller, the old depth is taken as the depth of the circuit block. As described above, the circuit block extraction processing is performed on the entire circuit, and the circuit block that is affected by the operation as the parameters are changed. To extract.

In the circuit of FIG. 5 (a), the paths are not searched redundantly, but as shown in FIG. 5 (b), the paths and circuits of the circuit block A-circuit block B-circuit block C are searched. When there is a path of block A-circuit block E-circuit block C, the circuit block E is selected twice. In such a case, the circuit block E may be selected twice. In such a case, the depths in each pass are compared and the minimum depth is selected.

FIG. 6 shows an algorithm of the circuit block extraction unit of the present invention. The circuit parameter is changed in the circuit block C of FIG. 5A, and the algorithm will be described according to the step number of FIG. 6 with the reference value for the depth judgment being 1 (see FIGS. 4 and 5).

The circuit block including the S1 parameter changing element is detected (in this case, the circuit block C). S2, S3 Search for adjacent circuit blocks (circuit block B and circuit block E are obtained with circuit block C as a parent). If there is a circuit block, the process proceeds to S4, and if not, the process proceeds to S12.

If there is an S4 circuit block, one of the circuit blocks is selected and the rest is held in the stack 44. In this case, it is assumed that the circuit block B is selected and the circuit block E is held in the stack 44.

S5 The depth of the circuit block is obtained (the depth of the circuit block B is calculated and the depth is set to 1). S6 It is determined whether the depth is within the reference depth (reference value). If the reference depth is satisfied, the process proceeds to S7, and if not satisfied, the process proceeds to S12 and is extracted from the stack 44. In this case, the reference depth of the circuit block B is 1, and since the circuit block B satisfies the reference depth, the process proceeds to S7.

S7, S8 It is determined whether a path search has been executed in the past. If it is not a pass executed in the past, proceed to S9,
If it has been executed in the past, the process proceeds to S10. In this case, since the block B is the circuit block on the first path, the process proceeds to S9 and the extraction process is performed.

Since it is found in S9 and S8 that the path has not been executed in the past, this circuit block is extracted as a circuit block affected by the parameter change, the process returns to S2, and the processes after S2 are repeated. In this case, the circuit block B is extracted, and the process returns to S2.

The adjacent circuit block of the circuit block (circuit block B) extracted in S2, S3 and S9 is searched. In this case, the adjacent circuit block of the circuit block B is the circuit block A, so that it is selected. Then, the circuit block A is found and there is no other adjacent circuit block (C is not selected because it has been processed).
In step S5, the depth of the circuit block is obtained. Circuit block A is a fan-in block of circuit block B,
Since the depth of the parent circuit block B is 1, the circuit block A
The depth of is 2. Then, in S6, the depth is compared with the reference depth. The depth reference depth is 1, so it is not selected. Therefore, the process proceeds to S12.

S12, S13 A circuit block is extracted from the stack 44. If there is a circuit block in the stack 44, the process proceeds to S5, and if not, the process ends. Since the circuit block E is currently stored in the stack 44, the circuit block E is extracted. Then, in S5, the depth of the circuit block E is determined. Circuit block E is circuit block C
(Depth 0), and since it is the fan-in block, the depth is 1. Then, in S6, the depth is determined. Since the depth is within the reference depth, it is determined in S8 whether the path has been executed (searched) in the past. Since it is not the path searched in the past, the circuit block E is extracted in S9. To do.

Returning to S2, the circuit block E just processed
The adjacent circuit block of is searched. Since the adjacent circuit blocks of the circuit block E are the circuit block D and the circuit block F, one of them, for example, the circuit block F is selected and the circuit block D is stored in the stack 44. After that, the processes from FIG. 5 onward are repeated. In the process of the processing, the circuit block F is a fanout of the parent circuit block E, so the depth is set to the same depth 1 as the circuit block E. Therefore, the search of S6 proceeds to S7, and since there is no path searched for in the circuit block F in the past, the determination of S8 proceeds to S9 and is selected. Returning to S2, the same processing is repeated for the adjacent circuit block H of the circuit block F.

In FIG. 5 (a), it is assumed that the search has been executed in the past in S7 and S8.
Although there is no circuit block that receives the processing to proceed to 11, FIG.
In the case of (b), since the circuit block E is searched twice when the reference depth is 2, in such a case S1
At 0 and S11, the depths of old and new are determined. If the old one is smaller, the processing from S12 is repeated without adopting the new depth, and if the new one is smaller, the circuit block is extracted in S9.

When the stack becomes empty in S13, the circuit block extraction processing is terminated. FIG. 7 is an operation explanatory diagram of the embodiment of the system configuration of the circuit simulation apparatus of the present invention.

In FIG. 7, 12 'is a circuit data holding unit. Reference numeral 13 is a simulation execution unit.

Reference numeral 13 'is a simulation controller.
Reference numeral 14 is a partial circuit extraction unit. Reference numeral 15 is a circuit information holding unit.

Reference numeral 16 is an extraction circuit holding unit. Reference numeral 17 is a simulation result output unit. Reference numeral 18 is an input / output control unit.

Reference numeral 31 denotes an interface with an input / output device, which exchanges information with external devices such as a keyboard, a mouse, and a magnetic disk device. Reference numeral 31 is an extraction circuit.

Reference numeral 82 is an input signal, which is a signal input from an external terminal. In the extraction circuit holding unit 16, 7
Reference numeral 1 is an extraction block.

In the circuit information holding unit 15, 72 is element information. Reference numeral 73 represents a net list.

74 is a parameter. 75 is a simulation result. The operation of the configuration of FIG. 7 will be described.

Input data (netlist,
Enter device information, etc.). In the case of performing a simulation with a plurality of circuit parameters for the same circuit element, first, the simulation is performed for the entire circuit with respect to one parameter. The simulation result is held in the circuit information holding unit 15.

Next, when performing a simulation with respect to another circuit parameter (change parameter), the partial circuit extracting unit 14 obtains a circuit block whose circuit parameter has been changed, and a circuit affected by the change of the parameter of the circuit block. Extract blocks. Then, a net which is a boundary between the extracted partial circuit which is the input terminal of the extracted partial circuit and the rest of the circuits is obtained. The net is treated as an external input terminal for the extracted partial circuit, and the signal output to the net in the initial simulation is used as the input signal of the extracted partial circuit. Similarly, each time the parameter value is changed, the partial circuit affected by the change is extracted, and the simulation is executed only on the extracted partial circuit.

FIG. 8 shows an algorithm for executing the circuit simulation having the configuration of FIG. 7 (refer to FIG. 7 in the description of FIG. 8). S1 Read input data from the external input device.

S2 The initial simulation is executed, and the simulation result is held in the circuit information holding unit 15.
The simulation result is output to an external device (display, printer, magnetic disk device, etc.).

The S3 partial circuit extracting section 14 determines the circuit block including the circuit element whose parameter has been changed, and extracts the range affected by the parameter changing element of the circuit block.

S4 The simulation execution unit treats the connection net of the extraction circuit and the rest of the circuits as an external input terminal of the extracted circuit. S5 Change element parameters.

S6 The simulation executing unit 13 executes a circuit simulation on the extraction circuit. For a terminal whose external input terminal is the connection net of the extracted partial circuit and the rest of the circuit, the signal appearing on that net in the initial simulation is used as the input signal for that terminal.

S7 The simulation result is held in the circuit information holding unit 15, and is output from the simulation result output unit 17 to the external device. FIG. 9 is an example of a circuit that executes the circuit simulation of the present invention.

In FIG. 9, the solid line indicates the circuit block A,
C, D, F, G, I and J are shown. Dotted line is circuit block B
Is shown.

Coarse dotted lines indicate the circuit blocks E and K. The fine dotted line indicates the circuit block H. n1 is an input terminal of the circuit block A.

Reference numeral n2 is an input terminal of the circuit block D.
Reference numeral n3 is an output net of the circuit block H, which is a net giving an input signal of the circuit block F.

VCC is a power supply terminal, and VSS is a ground terminal. A simulation analysis is performed for the case where the capacity of C1 is changed to three values of 0.1, 0.2, and 1.0.

First, the circuit is divided into blocks. Here, the block is divided into elements and nodes that are coupled by the channel and capacitance of the transistor. However, the constant voltage source VCC and the ground terminal VSS are all disconnected and do not belong to any block. By the circuit division as described above, the circuit block is divided into 11 blocks of A to K. Figure 5 (a) shows the connection between blocks only.
It becomes (as described above).

First, simulation is performed for all circuits with the capacitance value of C1 set to 0.1. Then, this simulation result is held. Next, a circuit block is extracted as a circuit block affected by the element C1 according to the above-described circuit block extraction method. If the depth of the circuit block C is 0 with reference to the block C, the blocks B, E, and F are 1, block A, D, H, and I are 2.
Since G and K are 3 and J is 4, the depth reference value is set to 1, and four blocks of circuit blocks B, C, E, and F are selected. For the circuit composed of these four blocks, n1, n2, n3, VCC, VSS are used as input terminals.
There are five. Of these, the original external terminals n1, n2
A signal is input using n3 as a new external terminal. At this time, the input signal of n3 uses the signal obtained as the simulation result in the result of the previous simulation.

For example, if the signal change shown in FIG. 10 appears at n3 in the overall circuit simulation, the signal shown in FIG. 10 is input to the input terminal n3 of the extraction circuit block (B, C, E, F). The simulation is performed as a thing.

[0072]

According to the present invention, high-speed circuit simulation can be performed when the parameters of the circuit element are changed to a plurality of values. Therefore, the efficiency of circuit simulation can be significantly improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is an operation explanatory diagram of a partial circuit extraction unit in the basic configuration of the present invention.

FIG. 3 is a diagram showing an example of a system configuration of a circuit simulation device of the present invention.

FIG. 4 is a functional block diagram of a partial circuit extraction process of the present invention.

FIG. 5 is a diagram showing an example of circuit connection.

FIG. 6 is a diagram showing an algorithm of a circuit block extraction unit of the present invention.

FIG. 7 is an operation explanatory diagram of the embodiment of the system configuration of the circuit simulation apparatus of the present invention.

FIG. 8 is a diagram showing an algorithm for executing a circuit simulation according to the present invention.

FIG. 9 is a diagram showing an example of a circuit that executes the circuit simulation of the present invention.

FIG. 10 is a diagram showing an example of signals obtained by circuit simulation.

[Explanation of symbols]

 1: Circuit simulation device 2: Circuit information input unit 3: Data storage unit 4: Circuit information storage unit 5: Simulation result storage unit 6: Partial circuit extraction unit 8: Simulation execution unit 9: Simulation result output unit

Claims (3)

[Claims] 1. A circuit simulation apparatus comprising a simulation execution unit and a circuit information holding unit for holding circuit information, and performing circuit simulation based on circuit parameters, when circuit parameters are changed,
A circuit simulation device comprising a partial circuit extracting unit for obtaining a partial circuit affected by a change in a circuit parameter, and performing circuit simulation only on the extracted partial circuit when the circuit parameter is changed. 2. When the extracted circuit is B, the remaining extracted circuit is A, and the connection net of the circuit A and the circuit B is N,
2. The net N as an input terminal of the circuit B after changing the circuit parameter, and the signal appearing on the net N before changing the circuit parameter as an input signal of the circuit B after changing the circuit parameter. Circuit simulation device. 3. The partial circuit extraction unit divides a circuit into blocks, and when a block including an element whose circuit parameter is changed is used as a reference block, obtains a path from the reference block to another circuit block, and the path is obtained. When is traced from the reference block, the inter-block paths from the fan-out block to the fan-in block are counted, and the number is defined as the depth from the reference block to the corresponding circuit block,
3. The circuit simulation device according to claim 1, wherein a circuit block whose depth is smaller than a predetermined constant value is extracted as a circuit block affected by the change of the circuit parameter.