JPS57178518A - Interruption control circuit - Google Patents

Interruption control circuit

Info

Publication number
JPS57178518A
JPS57178518A JP6307681A JP6307681A JPS57178518A JP S57178518 A JPS57178518 A JP S57178518A JP 6307681 A JP6307681 A JP 6307681A JP 6307681 A JP6307681 A JP 6307681A JP S57178518 A JPS57178518 A JP S57178518A
Authority
JP
Japan
Prior art keywords
interruption
intn
priority
signal
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6307681A
Other languages
Japanese (ja)
Inventor
Yuji Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP6307681A priority Critical patent/JPS57178518A/en
Publication of JPS57178518A publication Critical patent/JPS57178518A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To perform prescribed processing by deciding on priority through simple operation by inputting plural interruption signal OR signal and the conditions of interruption signals to a micro-processor, and determining the priority of each interruption signal through software on a processor side. CONSTITUTION:An OR signal regarding interruption signals INT1-INTn is supplied to the interruption signal input terminal of a micro-processor CPU2 through an NOR gate 1. Further, addresses of the high and low bits of jump instructions JP from buffer circuits 3, 4 and 5 and the conditions of the signals INT1-INTn are applied to a memory 7 to obtain combinations of the signals INT1-INTn for simultaneous generation, and information on the priority of the signals INT1-INTn is outputted in accordance with the combinations. In the 1st stage of interruption response, the CPU2 reads the outputs of the circuits 3-5 and then reads said information on priority from the memory 7, thereby performing interruption response processing regarding the simultaneously- generated signals INT1-INTn by referring to the information.
JP6307681A 1981-04-24 1981-04-24 Interruption control circuit Pending JPS57178518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6307681A JPS57178518A (en) 1981-04-24 1981-04-24 Interruption control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6307681A JPS57178518A (en) 1981-04-24 1981-04-24 Interruption control circuit

Publications (1)

Publication Number Publication Date
JPS57178518A true JPS57178518A (en) 1982-11-02

Family

ID=13218879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6307681A Pending JPS57178518A (en) 1981-04-24 1981-04-24 Interruption control circuit

Country Status (1)

Country Link
JP (1) JPS57178518A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355653A (en) * 1989-06-16 1991-03-11 Internatl Business Mach Corp <Ibm> System and method for interrupt processing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355653A (en) * 1989-06-16 1991-03-11 Internatl Business Mach Corp <Ibm> System and method for interrupt processing

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