KR910008254Y1 - Circuit for expanding capacity of dmac - Google Patents

Abstract

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Description

Capacity Expansion Circuit of Direct Memory Access Controller

1 is a conventional circuit diagram.

2 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

200: CPU 201: memory

220: DMAC 230: address decoder

240-243: 1-4 buffer circuit 250: logical multiplication device

251: inverting element 252-254: logic element

The present invention relates to a direct memory access controller that relays a central processing unit (CPU) and a memory in a digital processing apparatus. In particular, the present invention relates to a direct memory access controller capable of relaying a large CPU and a memory. There is an excessive amount of circuitry to confirm the relay capability.

Generally, a digital processing apparatus includes a CPU and a memory, and a direct memory access controller (DMAC) for relaying data between the CPU and the memory.

Recently, a data processing apparatus capable of processing a large amount of data has emerged, and for this reason, a large CPU and a large memory are required to process the large amount of data.

Therefore, as the capacity of CPU and memory increases, the relay capacity of DMAC must increase.

However, since the DMAC having a large relay capacity has not been developed, a large CPU 100 is used as shown in FIG. 1, but the capacity of the DMAC 110 and the memory 120 should be used as much as that of the existing one. This is because there is no large relay capacity of the DMAC (110).

In other words, while the CPU 100 processes 32 bits of data, the DMAC 110 and the memory 120 use those that cannot accommodate 16 bits of data. After all, this is limited because the relay capability of the DMAC 110 is 16 bits.

Accordingly, an object of the present invention is to provide a capacity determining circuit of a DMAC capable of relaying a large amount of CPU and memory by a small amount of DMAC in a digital processing apparatus.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of the present invention, in the data processing apparatus having a large capacity CPU 200 and memory 210, a small capacity DMAC 220, and an address decoder 230, the CPU 200 and the memory ( A data passage means comprising a plurality of buffer circuits 240-243 for relaying the data amount between the 210 and the DMAC 220 by a predetermined amount, and the address of the CPU 220 and the address decoder 230. In order to control the operation of the plurality of buffer circuits 240-243, respectively, by an output and a data bus control signal of the DMAC 220, a logical multiplication device 250, an inversion device 250, and three logical sum devices 252. A data path control means composed of -254).

Therefore, the present invention will be described in detail with reference to FIG.

Before describing the present invention, it is assumed that the CPU 220 is a 32-bit processor and the DMAC 220 is a 16-bit DMAC, and the buffer circuits 240-243 are each assumed to be an 8-bit buffer circuit.

Therefore, the data bus between the CPU 220 and the memory 210 becomes a 32-bit bus line. For convenience, the most significant 8 bits are referred to as the most significant bus (hereinafter referred to as DUM) and the next higher 8 bits are referred to as the next higher bus (hereinafter referred to as CUU) and the least significant 8 bits. The lowermost bus (hereinafter referred to as DLL) and the next lower 8 bits are set to the next lower bus (hereinafter referred to as DLM).

The data path means composed of four buffer circuits 240-243 relays data transfer between the CPU 220 and the DMAC 220 or between the memory 210 and the DMAC 220. The first buffer 24 is a DLL. The lower 8-bit data port (hereinafter referred to as DLD) of the DMAC 220 and the second buffer 241 are the upper 8-bit data port (DDD) of the DLM DMAC 220, and the third buffer 242 represents a DUM. The DLD of the DMAC 220 and the fourth buffer 243 relay the DUU with the DUD of the DMAC 220.

The data path control means for controlling the data path includes a logical multiplication device 240, an inverting device 251, and three logical sum devices 252-254. The logic-junction element 252 outputs the output of the address decoder 230, the data bus control signal of the DMAC 220 (hereinafter referred to as DBEN), and the inverted least significant address (hereinafter referred to as Al) introduced through the inversion element 251. A logic enable operation signal for enabling the first and second buffer circuits 240 and 241 to operate the first and second buffer circuits 240 and 241 when all the input signals are in the low logic state is the first and second buffer circuits 240 and 241. Supplies). And the logical sum element 253 of the DMAC 220. And an A1 introduced through the inverting element 251, and the logical sum element 254 is configured to output the address decoder 230 and the DMAC 220. Calculates OR. Then, the AND device 250 performs an AND operation on the outputs of the two OR devices 253 and 254, and if any one of the outputs of the OR devices 253 and 254 is in a low logic state, the third and fourth buffers. A buffer enable signal of a low logic state for operating the circuits 242 and 243 is supplied to the third and fourth buffer circuits 242 and 253.

As a result, when the first and second buffer circuits 240 and 241 and the third and fourth buffer circuits 242 and 243 are operated, the truth table 1-1 is expressed.

Truth Table 1-1

Since the interaction relationship between the CPU 220, the address decoder 230, the memory 210, and the DMAC 220 is well known in general, the description thereof has been omitted.

As described above, the present invention connects the DMAC to a large capacity CPU and memory through a plurality of buffer circuits, and separate data for connecting the buffer circuits to the CPU and memory and operating the buffer circuits whenever the CPU and the DMAC operate. By controlling the passage, there is an advantage in extending the relay capability of the DMAC.

Claims (1)

In a data processing apparatus including a large CPU 220 and a memory 210, a small DMAC 220, and an address decoder 230, the data amount between the CPU 220 and the memory 210 is divided by a predetermined amount. The data passage means for relaying with the DMAC 220, the address of the CPU 220, the output of the address decoder 230, and the data bus control signal of the DMAC 220. A capacity expansion circuit of a direct memory access controller, characterized in that it comprises a data path control means for controlling the relay of the controller.