JP2970227B2 - Multi-stage logic optimizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for optimizing a logic circuit. In particular, it relates to means for optimizing multi-stage logic.

[0002]

2. Description of the Related Art Conventionally, a multi-stage logic optimizing device of this kind has
After enumerating the factor candidates of the target circuit, the optimal factor was determined only by the area cost and the delay cost of these factors themselves.

[0003]

In such a conventional example, the optimum factor is determined only by the area cost and the delay cost of the factor itself, and the wiring cost when the factor is adopted is not taken into consideration. However, there is a disadvantage that the area or the delay due to the above-mentioned problem increases to a considerable extent, and as a result, an optimum circuit cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-stage logic circuit optimizing apparatus which eliminates such a drawback and has means for further reducing the circuit area and increasing the speed.

[0005]

SUMMARY OF THE INVENTION The present invention provides a constraint input means for storing a constraint including a signal arrival time at a given input terminal and a signal request time at an output terminal, and a multi-stage logic optimization target circuit. Factor candidate enumeration means for enumerating the factor candidates of the above, cost calculation means for calculating the area cost and the delay cost of the factor candidates enumerated by the factor candidate enumeration means based on the constraints stored in the constraint condition input means, Factor deciding means for deciding a factor whose total cost is optimal among the factor candidates enumerated by the factor candidate enumerating means, and ending adopting this factor when the factor decided by this factor deciding means exceeds a predetermined threshold value A logic optimizing device comprising: a determination unit; and a factor substitution unit that changes a circuit configuration by applying the factor adopted by the end determination unit to the multi-stage logic circuit. The area cost and / or the delay cost of the wiring are calculated based on the number of fanouts of the factor candidates enumerated by the child candidate enumeration means, and the result obtained by adding the cost obtained by the cost calculation means to the wiring cost which is the sum of the calculation results is obtained. It is characterized by having a wiring cost calculating means for generating as a total cost.

[0006]

The optimum factor is determined in consideration of the wiring cost in addition to the area cost and the delay cost of the factor itself. As a result, it is possible to avoid that the area or delay due to the wiring is increased to a level that cannot be ignored, and as a result, an optimum circuit cannot be obtained.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing this embodiment.
In this embodiment, constraint condition input means 1, factor candidate enumeration means 2, area cost calculation means 3, delay cost calculation means 4, wiring cost calculation means 5, factor determination means 6, end determination means 7
And factor substitution means 8. Referring to FIG. 2, the wiring cost calculating means 5 includes a fan-out number calculating means 21, a wiring area cost calculating means 22, a wiring delay cost calculating means 23, and a wiring cost adding means 24. That is, this embodiment is different from the embodiment shown in FIGS.
Alternatively, as shown in FIG. 3, a constraint condition input means 1 for storing constraint conditions including a signal arrival time at a given input terminal and a signal request time at an output terminal, and a multi-stage logic circuit to be optimized. Factor candidate enumeration means 2 for enumerating factor candidates, and cost calculation means for calculating the area cost and the delay cost of the factor candidates enumerated by the factor candidate enumeration means 2 based on the constraints stored in the constraint condition input means 1. Area cost calculation means 3 and delay cost calculation means 4, factor determination means 6 for determining the optimum factor among the factor candidates enumerated by factor candidate enumeration means 2, and factor determination means 6 determining the total cost. When the factor exceeds a predetermined threshold, the end determining means 7 adopts this factor, and the factor adopted by the end determining means 7 is applied to the multi-stage logic circuit to change the circuit configuration. And a factor assignment means 8 for further as a means which is a feature of the present invention, the area cost and or delay costs for wiring calculated based on the number of fan-out of the listed factors candidates factor candidate enumeration means 2,
There is provided a wiring cost calculating means 5 for generating a result obtained by adding a cost obtained by the cost calculating means to a wiring cost which is a sum of the calculation results as a total cost.

Next, the operation of this embodiment will be described with reference to the drawings. When constraint conditions such as the arrival time of a signal at an input terminal and the request time of a signal at an output terminal are input, the constraint condition input means 1 converts this into an internal data structure and stores it. Next, the factor candidate listing means 2 lists the factor candidates of the target circuit. The area cost calculation means 3 and the delay cost calculation means 4 calculate the area cost and the delay cost of these factor candidates based on the constraint condition. Next, the wiring cost calculation means 5 calculates the fanout number of each factor by the fanout number calculation means 21. Based on this, the wiring area cost calculation means 2
Reference numeral 2 denotes a wiring area cost based on a calculation formula estimated in advance for each technology, and similarly, a wiring delay cost calculation unit 23 calculates a wiring delay cost. The wiring cost adding means 24 calculates the total cost in addition to the costs relating to these wirings, in addition to the costs obtained by the area cost calculating means 3 and the delay cost calculating means 4. The factor determining means 6 selects an optimal one of the total costs from the factor candidates and determines it as a factor. Next, the end determination means 7 checks whether or not the cost of the determined factor satisfies a specific threshold value. If the cost is satisfied, the factor determination means 8 actually substitutes the factor into the target circuit by the factor substitution means 8. The configuration is changed, and the processing from the factor candidate listing means 2 is repeated. If the condition is not satisfied, it is determined that further multi-stage processing is impossible, and the process is terminated.

FIG. 3 is a block diagram of an embodiment in which the wiring cost calculating means 5 of the embodiment shown in FIG. 2 is realized by another means. The fan-out number calculating means 31, the wiring delay cost calculating means 3
2. It is composed of wiring cost adding means 33. In this embodiment, the calculation of the wiring cost is performed only by the delay cost. Further, the calculation of the wiring cost can be performed only by the area cost.

[0010]

According to the present invention, as described above, the area of the circuit after multi-stage logic optimization can be reduced by considering the wiring cost when the factor is employed in addition to the cost of the factor itself. This has the effect of increasing the speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a first configuration of a wiring cost calculation unit included in FIG. 1;

FIG. 3 is a diagram showing a second configuration of the wiring cost calculation means included in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Constraint condition input means 2 Factor candidate enumeration means 3 Area cost calculation means 4 Delay cost calculation means 5 Wiring cost calculation means 6 Factor determination means 7 Termination determination means 8 Factor substitution means 21, 31 Fanout number calculation means 22 Wiring area cost calculation Means 23, 32 Wiring delay cost calculating means 24, 33 Wiring cost adding means

Claims (1)

(57) [Claims] 1. Constraint condition input means for storing constraint conditions including a signal arrival time at a given input terminal and a signal request time at an output terminal, and enumerate factor candidates of a multistage logic circuit to be optimized. Factor calculating means for calculating the area cost and the delay cost of the factor candidates enumerated by the factor candidate enumeration means based on the constraint conditions stored in the constraint condition input means, and the factor candidate enumeration means A factor determining means for determining a factor whose total cost is optimal among the factor candidates enumerated in the above, an end determining means for adopting this factor when the factor determined by the factor determining means exceeds a predetermined threshold, A logic substituting means for applying a factor adopted by the end determining means to the multi-level logic circuit to change a circuit configuration; Calculate the area cost and / or delay cost related to the wiring based on the number of fan-outs of the factor candidates listed in the column, and add the cost obtained by the cost calculating means to the wiring cost which is the sum of the calculation results as a total cost. A multi-stage logic optimizing device comprising a wiring cost calculating means for generating.