JPH05342302A - Multilevel logic optimizing device - Google Patents

Abstract

PURPOSE:To reduce the circuit area and to increase the calculation speed by determining an optimum factor in consideration of not only the area cost of the factor itself and the delay cost but also the wiring cost. CONSTITUTION:A factor candidate enumerating means 2 enumerates factor candidates of an object circuit. An area candidate calculating means 3 and a delay cost calculating means 4 calculate area costs and delay costs of these factor candidates by constraint conditions. A wiring cost calculating means 5 calculates the fan-out number of each factor by a fan-out number calculating means, and a wiring area cost calculating means calculates the area cost of wiring based on this fan-out number in accordance with a calculation formula preliminarily estimated for each technology, and a wiring delay cost calculating means calculates the delay cost of wiring in the same manner. A wiring cost adding means adds these costs related to wiring to costs obtained by the area cost calculating means 3 and the delay cost calculating means 4 to calculate the total cost. A factor determining means 6 selects and determines one having the optimum total cost out of factor candidates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for optimizing logic circuits. In particular, it relates to optimization means for multi-level logic.

[0002]

2. Description of the Related Art Conventionally, this type of multistage logic optimizing device is
After enumerating the candidate factors of the target circuit, the optimum factor was determined only by the area cost and delay cost of these factors themselves.

[0003]

In such a conventional example, the optimum factor is determined only by the area cost and delay cost of the factor itself, and the wiring cost when the factor is adopted is not taken into consideration. However, there is a drawback in that the area or the delay due to is increased to a non-negligible amount, and as a result, an optimum circuit may not be obtained.

An object of the present invention is to eliminate such drawbacks and to provide a multi-stage logic circuit optimizing device having means capable of further reducing the circuit area and increasing the speed.

[0005]

According to the present invention, there is provided constraint condition input means for storing constraint conditions including a signal arrival time at a given input terminal and a signal request time at an output terminal, and a multi-stage logic optimization target circuit. Factor candidate enumerating means for enumerating the factor candidates, cost calculating means for calculating area cost and delay cost of the factor candidates enumerated by the factor candidate enumerating means based on the constraint condition stored in the constraint condition inputting means, and Factor determining means for determining the factor with the optimum total cost among the factor candidates listed by the factor candidate listing means, and adopting this factor when the factor determined by this factor determining means exceeds a predetermined threshold value. A logic optimizing device comprising: a determining means; and a factor substituting means for applying a factor adopted by the end determining means to the multi-stage logic circuit to change a circuit configuration, The area cost and / or the delay cost related to the wiring are calculated based on the fan-out numbers of the factor candidates listed by the child candidate listing means, and the result obtained by adding the cost obtained by the cost calculating means to the wiring cost which is the sum of the calculation results is calculated. It is characterized in that it is provided with a wiring cost calculation means for generating it as a total cost.

[0006]

The optimum factor is determined in consideration of the area cost and delay cost of the factor itself and the wiring cost. As a result, it is possible to prevent the area or delay due to the wiring from increasing so much that it cannot be ignored, and as a result, the optimum circuit cannot be obtained.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing this embodiment.
In this embodiment, constraint condition input means 1, factor candidate enumeration means 2, area cost calculation means 3, delay cost calculation means 4, wiring cost calculation means 5, factor determination means 6, end determination means 7
And factor substitution means 8. Referring to FIG. 2, the wiring cost calculation means 5 is composed of a fanout number calculation means 21, a wiring area cost calculation means 22, a wiring delay cost calculation means 23, and a wiring cost addition means 24. That is, this embodiment is similar to FIG.
Alternatively, as shown in FIG. 3, a constraint condition input means 1 for storing constraint conditions including a signal arrival time at a given input terminal and a signal request time at an output terminal, and a multi-stage logic circuit to be optimized. A factor candidate enumeration unit 2 that enumerates the factor candidates and a cost calculation unit that calculates the area cost and delay cost of the factor candidates enumerated by the factor candidate enumeration unit 2 based on the constraint condition stored in the constraint condition input unit 1. The area cost calculating means 3 and the delay cost calculating means 4, the factor determining means 6 for determining the optimum factor of the total cost among the factor candidates listed by the factor candidate listing means 2, and the factor determining means 6. When the factor exceeds a predetermined threshold value, the end determination means 7 that employs this factor, and the factor adopted by this end determination means 7 are applied to the multi-stage logic circuit to change the circuit configuration. And a factor assignment means 8 for further as a means which is a feature of the present invention, the area cost and or delay costs for wiring calculated based on the number of fan-out of the listed factors candidates factor candidate enumeration means 2,
The wiring cost calculation means 5 is provided for generating the total cost by adding the cost obtained by the cost calculation means to the wiring cost which is the sum of the calculation results.

Next, the operation of this embodiment will be described with reference to the drawings. When a constraint condition such as a signal arrival time at the input terminal and a signal request time at the output terminal is input, the constraint condition input means 1 converts the constraint condition into an internal data structure and stores it. Next, the factor candidate listing means 2 lists the factor candidates of the target circuit. The area cost calculation means 3 and the delay cost calculation means 4 calculate the area cost and delay cost of these factor candidates based on the constraint conditions. Next, the wiring cost calculation means 5 calculates the fanout number of each factor by the fanout number calculation means 21. Based on this, the wiring area cost calculation means 2
Reference numeral 2 calculates the wiring area cost from the calculation formula estimated in advance for each technology, and similarly, the wiring delay cost calculation means 23 calculates the wiring delay cost. The wiring cost adding means 24 adds the costs related to these wirings to the costs obtained by the area cost calculating means 3 and the delay cost calculating means 4, and calculates the total cost. The factor determining means 6 selects an optimal total cost from the factor candidates and determines it as a factor. Next, the end judging means 7 checks whether or not the cost of the decided factor satisfies a specific threshold value, and if it does, the factor substituting means 8 actually substitutes the factor into the target circuit to make the circuit. The configuration is changed and the processing from the factor candidate listing means 2 is repeated. If not satisfied, it is determined that further steps cannot be performed, and the process ends.

FIG. 3 is a block diagram of an embodiment in which the wiring cost calculation means 5 of the embodiment shown in FIG. 2 is realized by another means. The fanout number calculation means 31 and the wiring delay cost calculation means 3 are shown.
2. Wiring cost adding means 33 is included. In this embodiment, the wiring cost is calculated only by the delay cost. Further, the wiring cost can be calculated only by the area cost.

[0010]

As described above, the present invention makes it possible to further reduce the area of the circuit after the multi-stage logic optimization by considering the wiring cost when the factor is adopted in addition to the cost of the factor itself. , There is an effect that the speed can be made faster.

[Brief description of drawings]

FIG. 1 is a diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a first configuration of a wiring cost calculation means included in FIG.

FIG. 3 is a diagram showing a second configuration of the wiring cost calculation means included in FIG.

[Explanation of symbols]

 1 constraint condition input means 2 factor candidate enumeration means 3 area cost calculation means 4 delay cost calculation means 5 wiring cost calculation means 6 factor determination means 7 end determination means 8 factor substitution means 21, 31 fanout number calculation means 22 wiring area cost calculation Means 23, 32 Wiring delay cost calculating means 24, 33 Wiring cost adding means

Claims (1)

[Claims] 1. A constraint condition input means for storing constraint conditions including a signal arrival time at a given input terminal and a signal request time at an output terminal, and factor candidates of a multi-stage logic circuit to be optimized. Factor candidate enumeration means, cost calculation means for calculating the area cost and delay cost of the factor candidates enumerated by the factor candidate enumeration means based on the constraint conditions stored in the constraint condition input means, and the factor candidate enumeration means Among the factor candidates listed in, the factor determining means for determining the optimal factor for total cost, and the termination determining means for adopting this factor when the factor determined by this factor determining means exceeds a predetermined threshold value, In the logic optimizing device provided with a factor substituting unit for changing the circuit configuration by applying the factor adopted by the end judging unit to the multi-stage logic circuit, The area cost and / or delay cost related to the wiring is calculated based on the fan-out numbers of the factor candidates listed in the column, and the result obtained by adding the cost calculated by the above cost calculation means to the wiring cost which is the sum of this calculation is taken as the total cost. A multi-stage logic optimizing device comprising a wiring cost calculating means for generating.