JPH05216956A - Optimizing approach for multistage logic circuit - Google Patents

Abstract

PURPOSE:To efficiently perform the logic synthesization and logic verification of a large-scaled circuit by utilizing a numbering approach optimum for the numbering of an input variable and expressing logic function by means of a dichotomizing determination graph having suppressed number of nodes, in the dichotomizing determination graph for expressing the logic function. CONSTITUTION:When the logic function to be outputted from a multi-output logic circuit is expressed with a common dichotomizing determination graph, the numbering approach utilizing the base separation method efficiently making the common use of the part graph of the dichotomizing determination graph in each output is adopted. Thus, the logic synthesization and logic verification of a large-scaled circuit, which has been considered to be impossible, can be efficiently performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of optimizing a multi-stage logic circuit, and more particularly to a method of expressing a logic function used when synthesizing or verifying a multi-stage logic circuit.

[0002]

2. Description of the Related Art Most of the ordering methods utilize connection information of a multi-stage logic circuit, and this method is the most effective method at present. As a conventional method, “Logic verification using a BDD in a logic synthesis environment (Logic Verifica
tion using Binary Decision Diagrams in a Logic Syn
thesis Environment) '' (In proceedings of the Interna
tional Conference on Computer-Aided Design, pp6-9,
1988) is a fan-in heuristic method.

The fan-in heuristic method will be briefly described. First, the external input and external output of the logic circuit are called primary input and primary output, respectively. The level of the primary output is 0, and the levels of the other gates are defined by the following equations. level (g _i ) = max (level (g _j )) + 1 where gate g _j is a fanout of gate g _i .
A transitive fan-in of a gate is a set of gates that have a path to the gate.

The method will be described below. First, find the level and transitional fan-in of all gates. At that time, the fan-in of the gate is decided not to have a communion with the transitive fan-in of each connected gate. Then, the gate is searched from the primary output to the primary input, that is, from the lower level to the higher level, and the higher order is given in the order in which the primary input appears. The search method is to search for the gate having the largest depth of the above-mentioned transitional fan-in among the gates connected to the fan-in of the gate with priority on the depth.

This technique is based on the following observations. First, the gate of the multi-stage logic circuit and the BDD are correlated. As shown in FIG. 5, the logic function y1 of the gate G1
Requires the information of a0, b0, c0, but the logic function y2 of the gate G2 requires the information of a0, b0, c0, a1, b1. Therefore, the following can be said in the BDD of FIG. The logical function y2 can be represented by a1, b1, and y1, but y1 requires information on a0, b0, and c0. That is, when using the information of a1 and b1, a0,
The information of b0 and c0 is required. Therefore a
It can be said that it is more efficient to place the order of 0, b0, c0 higher than a0, b0. However, this method aims only to minimize the number of nodes when expressing a logical function of a certain output of a logic circuit by a BDD, and shares the logical function of the output of a multi-output logic circuit with a BDD. It does not take into account the expression.

[0006]

When a logical function is represented by a BDD, the number of nodes depends largely on the ordering of input variables. There is a method as described above as a method of determining the optimum order of input variables. However, the method is intended only to minimize the number of nodes when expressing a logical function of a certain output of a logic circuit by a BDD, and express the logical function of the output of a multi-output logic circuit by a shared BDD. Not taking into account what to do. When the output of a multi-output multi-stage logic circuit is expressed by using a shared BDD, it is necessary to efficiently share the subgraphs of the BDD of the logical function of each output.

Therefore, an object of the present invention is to perform logic synthesis and logic verification of a large-scale circuit by expressing a logic function with a binary decision graph in which the number of nodes is suppressed to a low level by using an optimal ordering method for ordering input variables. It is to be able to do it efficiently.

[0008]

To achieve the above object, the present invention provides a binary decision graph of a logical function of each output when the output of a multi-output multistage logic circuit is represented by a shared binary decision graph. The trapezoidal division method is used as a method for efficiently sharing subgraphs. The platform division method is a method of dividing an input variable into subsets and performing ordering. The input variables belonging to each subset affect the set of logic functions of the same gate. Giving an adjacency order to input variables that belong to the same subset, and giving a lower order to input variables that affect the logic functions of many gates increases the likelihood of creating a subgraph that can be shared. It is based on the fact that input variables that affect many output logical functions are likely to represent sharable subgraph logical functions.

[0009]

With the ordering method of the present invention, the number of nodes in the shared BDD representing the logical function of the output of the multi-stage logic circuit can be minimized, and the logic synthesis and logic verification of a large-scale circuit can be efficiently performed. Become.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, some terms are introduced regarding a multi-stage logic circuit. After that, the ordering method is shown.

A "stand" is a set of input variables on which the logic function of a gate depends. A "partial platform" is a subset of platforms that are mutually exclusive, and all input variables belonging to a certain platform belong or do not belong to a platform.

The method according to the present invention will be described below with reference to FIG. Step 1: Determine the levels from the primary inputs of all gates of the multi-stage logic circuit. This is because it is considered that the complexity of the logic function increases as the distance from the primary input increases. With the level of the primary input set to 0, the levels of the other gates are defined by the following expressions.

Level (g _i ) = max (level (g _j )) + 1 However, the gate g _j is a fan-in of the gate g _i . Step 2: Build a platform for a given set of gates. The first is the set of gates furthest from the primary input.

Step 3: Build a set of sub-stands.

Step 4: Arrange the sub stand. Place the parts in order of decreasing number of gates that affect more. This is because an input variable that belongs to a sub stand having a large number of gates that have an influence is more likely to be an input variable that forms a shared subgraph. Here, the order of the input variables belonging to the sub stand having only one element is determined.

Step 5: The step 2 and the subsequent steps are applied to the sub stand having two or more elements. At this time, the set of gates used to newly construct the set of stages is a set of gates whose level is close to the primary input by one.

Step 6: The ordering of all the input variables is completed when the ordering in all the sub-tables is completed, that is, the number of elements in all the sub-tables is one.

A specific example in which the above processing is applied to the multi-stage logic circuit of FIG. 2 will be described below. First, {g2, g3} is given as a set of gates. Gate g by step 2
The bases of 2 and g3 are {x1, x2, x3} and {x, respectively.
1, x2, x4}. Next, in step 3, the partial platform s1 is s1 = {x1, x2}, s2 = {x
3}, s3 = {x4}. Next step 4
Since the number of gates affected by the input variables belonging to the sub-slabs s1, s2, s3 is 2, 1, 1 respectively,
The order of the sub-stands is s2, s3, s1 (the order of s2, s3 is arbitrary). Finally, the order of the input variables is x3, x4,
x1, x2, and the binary decision graph as shown in FIG. 3 is obtained (the order of x1, x2 is arbitrary).

When the above-mentioned fan-in method is used for a similar multi-stage logic circuit, the order of the input variables is x1, x2,
x3 and x4 are obtained, and the binary decision graph as shown in FIG. 4 is obtained. Comparing the two, it can be seen that the number of nodes in FIG. 4 is 6 and the number of nodes in FIG. 3 is 4, and the binary decision graph of FIG. 3 efficiently shares the nodes.

[0020]

By using the input variable ordering method of the present invention, it is possible to reduce the number of nodes when expressing a multi-output logic function of a multi-stage logic circuit in a shared BDD. As a result, it becomes possible to efficiently perform logic synthesis and logic verification of a large-scale circuit, which was considered impossible in the past.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an input variable ordering method according to the present invention.

FIG. 2 is a diagram showing an example of a multi-stage logic circuit.

FIG. 3 is a diagram of an ordered binary decision graph of the input variables of the present invention.

FIG. 4 is a diagram of a BDD with input variables ordered using a conventional fan-in method.

FIG. 5 is an abstract representation of a multi-stage logic circuit.

FIG. 6 is a diagram in which the output of the circuit of FIG. 1 is represented by a BDD.

Claims (1)

[Claims] 1. A method for optimizing a multi-stage logic circuit using a shared BDD, wherein an input variable is divided into a subset by a platform division method.