JPH01279372A - Production of logic circuit - Google Patents

Abstract

PURPOSE:To realize the optimum allocation of optional parts when a gate logic is produced from a given Boolean formula by giving the shared information to the Boolean formula and allocating the parts while checking the correlation between Boolean formulas with said shared information used as a key. CONSTITUTION:A binary tree structure is formed for a Boolean formula according to the priority order of logical operators and then converted into a multi- split tree structure based on the number of fines of technology. Then the multi- split trees are integrated with the shared information used as a key and a parts which satisfies the designing limitation is retrieved out of a parts group 55 while transmitting successively the polarities to the input (or output) side from the output (or input) side of the multi-split tree structure. Thus a back (or front) tracking is carried out. A design rule group 56 of the technology is applied to a logic circuit obtained in such a way. Thus an optimum logic circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a logic circuit, and particularly to automation of logic design suitable for designing a digital system.

[Conventional technology]

Attempts to automatically generate gate logic from Boolean level functional logic have been made for a long time, and there are many known examples (for example, Japanese Patent Application Laid-Open No. 58-74971, or Japanese Patent Application No. 1983-1989).
233299), there is a problem in that the number of gates and the number of gate stages increases compared to when it is done by one person.

Conventionally, as described in the above-mentioned known example, optimal gate logic generation has been performed for a component group consisting of bipolar outputs (2-output component group) and a component group consisting of unipolar output (1-output component group). was.

[Problem to be solved by the invention]

The above conventional technology also realizes a method of optimally allocating a component group consisting of unipolar output (1-output component group) and a component group consisting of bipolar output (2-output component group) from the goal formula, but it is not possible to There was a problem in that the allocation of parts groups consisting of outputs (parts groups having two or more outputs) was not considered, and the parts groups to which the method could be applied were limited.

An object of the present invention is to provide a method for selecting and allocating optimal components from an arbitrary component group including multi-output components when generating gate logic from a given goal expression. [Means for Solving] The above object is achieved by assigning shared information to Boolean expressions in advance and realizing component allocation while examining correlations between Boolean expressions using this shared information as a key. This is a result of focusing on the fact that each output terminal of a logic circuit component can be logically expressed uniquely by the logic function of the input terminal, and that these logical expressions are not necessarily the same in multi-output components.

[Effect]

The shared information accompanying the Boolean expressions is given in advance by the logic designer. When one part is allocated, for the Boolean expressions having the shared information, a part that satisfies the function of the group of Boolean expressions is selected. On the other hand, for Boolean expressions that do not have shared information, components that satisfy the function of each Boolean expression are individually selected. The range of Boolean expressions to be expanded is determined by the presence or absence of shared information.

Therefore, under given conditions, it is possible to optimally allocate parts, including multi-output parts, so that deployment performance equivalent to manual deployment can be obtained.

〔Example〕

First, an example of a hardware configuration for carrying out the present invention will be described with reference to FIG. The input/output device 52 is used to input a functional logic diagram 51 expressing Boolean water, its output, and the polarity of variables to create a 1-function logic file 53. The processing device 54 stores the previously input functional logic file 53 and the technology component group 5 prepared in advance.
5 and a set of design rules 56 necessary for optimization of the technology, an output device 57 generates gate logic by performing the processing described below and converts the previously generated gate logic into a gate logic file 58. and is used to generate a gate logic diagram 59.

Next, an outline of the implementation procedure of the present invention will be explained. A two-tree structure is created for the Boolean expression according to the priority of logical operators, and it is converted into a multi-tree structure according to the fan-in number of the technology. Next, after integrating the multi-tree using the shared information as a key, parts that satisfy the design constraints are created as a group of parts while sequentially propagating the polarity from the output side (or input side) of the multi-tree structure to the input side (or output side). 55 and perform backward tracking (or forward tracking). In the logic @ path obtained by this ′
The design rule group 56 of the technology is applied to manufacture an optimal logic circuit.

Hereinafter, the implementation procedure of the present invention will be explained in detail. Note that since backward tracking and forward tracking are basically the same procedure, the following explanation will be limited to the procedure of backward tracking from the output side to the input side.

FIG. 1(a) is an example of a functional logic diagram describing a Boolean expression. Write the Boolean expression in a box, and write the output polarity of the Boolean expression and the polarity of the variable on the cut edge of the box. Variables that enter and exit the box via a circle indicate a negative pole, and variables that enter and exit a box without a circle indicate a positive pole.Shared information (hereinafter referred to as an expansion group number) is written at the beginning of the Boolean expression.

In this example, the Boolean expressions for output variables 01, 02, and 03 have expansion group number 1, and the Boolean expressions for output variables P1 and P2 have expansion group number 2.

For convenience, we will consider the Boolean expression as a positive logic expression, and the parts group as the basic parts of the technology shown in Figure 3. In the first step, output variables 01, 02, 03 . A binary tree structure is created by performing Borland transformation on each Boolean expression represented by PL and P2. This binary tree structure is shown in FIG. 1(b).

In the second step, on the binary tree structure created in the first step above, nodes with consecutive same logical operators are integrated within the maximum fan-in number of the parts group that can be supported by the technology. and convert it to a multi-tree structure. Specifically, since nodes 8 and 9 in FIG. 1(b) are nodes having consecutive logical product operators, these are converted into node 21 in FIG. 1(c). By applying similar processing to other nodes, the image shown in FIG. 1(b) can be converted into the image shown in FIG. 1(c).

In the third step, multitree integration is performed on the polygon Mizuhashi structure created in the second step, regarding polytree groups having the same expansion group number, while maintaining functional correspondence between nodes. Specifically, in the multitree group with expansion group number 1 in Figure 1(C) (multitree with output variables 01.02 and 03), nodes 21 and 23 have functional correspondences to nodes 24 and 25, respectively. Therefore, it is possible to perform main integration as shown in the left diagram of Figure 1(d). Similarly, the multitree group of expansion group number 2 can be integrated as shown in the right diagram of FIG. 1(d).

In the fourth step, the multi-tree +lv that has completed the multi-tree integration
! Convert the structure from the output node into a basic part that satisfies the design constraints. Specifically, the multitree shown in the left diagram of FIG. 1(d) has a logic function of AND-OR1, an output polarity of output node 29 is negative, a fan-in number of 2, and fans of input nodes 28 and 30. Since the number of inputs is 3 and the output polarity to the outside is positive in addition to the connection to the output side node 29, basic parts that satisfy these constraints are selected from the parts group in Figure 3 (constraints When there are a plurality of basic parts that satisfy the following, the priority order for parts selection is determined by (etc.), and the conversion is performed as shown in the left diagram of FIG. 1(e). Similarly, the multitree shown in the right diagram of FIG. 1(d) expressed by expansion group number 2 is converted into the basic component shown in the right diagram of FIG. 1(e).

In the fifth step, the input polarity of the basic component converted in the fourth step is set as the output polarity of the fan-in destination node.
Convert to basic parts in the same way as steps. Thereafter, the polarity is sequentially propagated to the input side and all nodes are converted into basic parts. Specific examples after this step will be omitted for convenience.

In the 6th step, the net structure of the basic component converted in the 5th step is checked for its primary input polarity and the corresponding input polarity of the box, and if there is a logical contradiction, an amplifier with matching polarity is inserted. .

In the seventh step, the logic circuit obtained in the sixth step is also subjected to circuit transformation based on design rules extracted in advance to generate an optimal logic circuit.

Although there is no correspondence with the basic parts shown in FIG. 3, FIG. 4 shows an example of a design rule for optimization.

According to this embodiment, it is possible to easily manufacture an optimal logic circuit.

〔Effect of the invention〕

According to the present invention, by adding shared information to Boolean expressions, any multi-output component can be selected from a group of Boolean expressions, and an optimal logic circuit can be generated. The generated logic circuit has development performance such as manual labor. In addition, since the processing procedure is relatively simple, it can be applied to the logical design process.
This reduces design man-hours and improves product quality.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the process of manufacturing a logic circuit using the present invention, Fig. 2 is a block diagram showing an example of a hardware configuration for implementing the present invention, and Fig. 3 is a diagram showing parts of specific technology. FIG. 4 is a diagram showing an example of a conversion rule for optimization of a certain technology. 1...Negative polarity, 2...Positive polarity, 3...Bipolarity, 4
...Input variable, 5...Output variable, 6...Development group number, 7...Boolean expression, 8-31...Node, 3
2 to 35... Basic parts, 52.57... Input/output device rt, 53... Functional logic file, 54... Data processing device, 55... Section, information. File, 56...Design rule file, 58...
Gate logic file. Agent Patent Attorney Elementary J11 Katsuy71 -NoS Houki 1 Figure 2 [Z] Early 3 Country

Claims (1)

[Claims] 1. When manufacturing functional logic expressed in Boolean expressions using logic circuits of a specific technology, there is a means for uniformly providing the output of the goal expression and the polarity of variables with positive or negative logic, and the same parts. A means of providing Boolean information for sharing, and fan-in numbers and
Fan-out number, power consumption, component delay, logic function (
(logical product, logical sum, etc.) and a means for uniformly expressing the polarity of input/output terminals in positive or negative logic and referring to this,
After converting the Boolean expression into a binary tree structure of operators and variables, a multi-tree structure conversion is performed by integrating operators within the range that can be mapped by the logic function of the technology, and the same parts added to the Boolean expression are The multi-tree structure is integrated based on the shared information of the Boolean expression, and the output polarity (or input polarity) of the Boolean expression is used as a key to find the parts that satisfy the logical function and output polarity (or input polarity) by referring to the parts list. Search, and use the input polarity (or output polarity) of the component found in this way as the output polarity (or input polarity) for the next component selection, and continue sequential backward (or forward) tracking until there are no unprocessed polygon trees. A method for manufacturing a logic circuit characterized by easily and optimally realizing a combinational circuit that satisfies a target Boolean expression by mapping a tree to parts. 2. It is characterized by comprising means for providing an optimal design rule for the technology, and realizing an optimal combinational circuit by applying the design rule as necessary in the process of mapping the multitree to a component. A method for manufacturing a logic circuit according to claim 1.