JPH06325121A - Logic simulation method - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of each processor by grouping respective future events based on the relation showing whether the future events can be processed in parallel among respective pipeline blocks and their internal and external events. CONSTITUTION:A logic circuit is inputted while divided into the pipeline blocks (S12), and events which can be processed in parallel among the internal events and external events generated in the logic circuit by the pipeline blocks are extracted (S13) and stored in a storage device. Then events having a reference time among the stored external events are transferred as one unit to a main storage memory (S15). Then the external events stored in the main storage memory and respective internal events generated in the logic circuit in the reference time corresponding to the respective events are taken out (S16) and the influence of the internal and external events to be exerted on the inside of the circuit in future is simulated in parallel by multiple processors S17 to find the future events.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for verifying the logic operation of a circuit when designing an LSI or the like.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a work flow of a logic simulation method for an LSI using, for example, a conventional multiprocessor computer. Hereinafter, a method of logic simulation will be described with reference to the drawings. First, the information of the logic circuit of the LSI for computer simulation is input (step S1) and stored in the storage device. Next, an external event input from the outside of the LSI is input (step S2) and stored in the storage device.

The information of the logic circuit input to the storage device as described above is transferred to the main storage memory (step S
3) is stored. Next, out of the external events stored in the storage device, a preset unit of reference time is transferred to the main storage memory (step S
4) Then memorize. Then, each external event stored in the main memory and each internal event generated in the logic circuit within the reference time corresponding to each external event are extracted (step S5), and each external event and each internal event are extracted. The influence of the event on the inside of the circuit in the future is simulated in parallel by the multiprocessor to obtain each future event (step S6).

Then, it is determined that future events occurring at the same time within the reference time can be processed in parallel, and these are grouped to form a future event group (step S
7) Then, it is stored in the simulation future event memory. Then, the future events included in each future event group are allocated to the multiprocessors and simulated in parallel (step S8).

Then, it is judged whether or not the preset maximum simulated time unit is exceeded, and if it is not exceeded, the reference time is incremented by one unit and the process returns to step S4 to perform the same operation as above again. Repeat the following simulation,
Hereinafter, this operation is repeated until the preset maximum simulated time unit is exceeded. If it exceeds, it is determined that the simulation is finished (step S9), and END is set.

[0006]

The logic simulation using the conventional multiprocessor computer is performed by the above method, and each future event occurs at the same time within the reference time. The future events included in each future event group are grouped into multiple processors, and the future events included in each future event group are allocated to multiple processors and simulated in parallel. However, there is a problem in that the utilization efficiency of each processor is deteriorated and the simulation time by parallel processing becomes long.

The present invention has been made in order to solve the above problems, and provides a logic simulation method capable of improving the utilization efficiency of each processor and shortening the simulation time by parallel processing. The purpose is to

[0008]

According to a logic simulation method of the present invention, a first step of dividing a logic circuit into pipeline blocks, each of which occurs in the logic circuit in each pipeline block. The second step of extracting those that can be processed in parallel from the internal event and each external event. Simultaneously simulating the effect of each external event on the inside with a multiprocessor to obtain each future event, and determining each future event. Based on the parallel processable relationship defined in the first and second steps, a third step for forming a future event group by dividing into groups every preset reference time, each future event The fourth step is to allocate the future events included in each group to the multiprocessors.

[0009]

According to the logic simulation method of the present invention, each future event is grouped based on the relationship between pipeline blocks, each pipeline block, each external event, and external events. The future event group is divided into groups, and the future event included in each future event group is allocated to the multiprocessor.

[0010]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows the LS using a multiprocessor computer
It is a figure which shows the work flow of the logic simulation method of I. Hereinafter, a method of logic simulation will be described with reference to the drawings. First, as in the conventional case, the logic circuit information of the LSI for computer simulation is input (step S10) and stored in the storage device. Next, the LS
An external event input from the outside of I is input (step S11) and stored in the storage device.

Then, the logic circuit is divided into pipeline blocks, which are input (step S12) and stored in a storage device. Then, among the internal events and the external events that occur in the logic circuit in each pipeline block, those that can be processed in parallel are extracted (step S13) and stored in the storage device. Then, as described above, step S10, step S12, and step S
Each information stored in the storage device by 13 is transferred to the main storage memory (step S14) and stored.

Next, of each external event stored in the storage device, one having a reference time as one unit is transferred to the main storage memory in advance (step S15) and stored. Then, each external event stored in the main memory and each internal event generated in the logic circuit at the reference time corresponding to each external event are extracted (step S1).
6) Then, the influence of each internal and external event on the inside of the circuit in the future is simulated in parallel by the multiprocessor (step S17), and each future event is obtained.

Then, future events occurring at the same time within the reference time, and steps 12 and 13
The future events having the relationship defined in 1. are judged to be capable of parallel processing, and these are grouped to form a future event group (step S18) and stored in the simulation future memory. Then, the future events included in each future event group are allocated to the multiprocessors and simulated in parallel (step S19).

Then, it is judged whether or not the preset maximum simulated time unit is exceeded, and if it is not exceeded, the reference time is incremented by one unit, the process returns to step S15, and the same operation as above is performed again. Repeat the following simulation,
Hereinafter, this operation is repeated until the preset maximum simulated time unit is exceeded. If it exceeds, it is determined that the simulation has ended (step S20), and END is set.

As described above, according to the first embodiment, the future event group is grouped based on the relationship between each pipeline block and each pipeline block, and whether external events can be processed in parallel. Since a large number of future events can be grouped into one future event group, the number of future events that can be assigned to the multiprocessor increases, and the utilization efficiency of the multiprocessor improves.

Example 2. In the first embodiment, step S1
Although 2 and step S13 are processed outside the software control means, the same effect as that of the above-described first embodiment can be obtained even if steps S12 and S13 are processed inside the software control means.

[0017]

As described above, according to the present invention, the first step of dividing a logic circuit into each pipeline block, each internal event generated in the logic circuit in each pipeline block, and each external. A second step of extracting those that can be processed in parallel from each other, simulating the influence of each external event and internal event on the inside by a multiprocessor in parallel, and obtaining each future event. Based on the parallel processable relationship defined in the second step, the third step for forming a future event group by dividing into groups within a preset reference time, and each future event group Since the fourth process for allocating future events included in each to each multiprocessor is provided, the utilization efficiency of each processor is improved and Simulation by physical - logical can save time for Deployment Simulation - Deployment method makes it possible to obtain.

[Brief description of drawings]

FIG. 1 is a diagram showing a work flow of a logic simulation method according to a first embodiment of the present invention.

FIG. 2 is a work flow of a conventional logic simulation method.
FIG.

[Explanation of symbols]

 S1-S20 steps

Claims (1)

[Claims] 1. A logic simulation method for inputting logic circuit information and an external event to perform simulation, the first step of dividing the logic circuit into each pipeline block, and each pipeline block. A second step of extracting each of the internal events generated in the logic circuit and the external events that can be processed in parallel for each internal circuit, and parallelizing the internal influence of the external events and the internal events. Each future event by simulating with a multiprocessor, and each future event is based on the parallel processable relationship defined in the first and second steps and every time within a preset reference time. The third step of forming a group of future events, and the future events included in each of the future event groups are divided into A logic simulation method, characterized in that each processor is provided with a fourth step.