JP2000269340A - Distributed failure simulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To average distributed failure simulation execution periods and sup press variations in simulation period by a method wherein a divided failure list is prepared in response to failure simulation processing capacity of a plural ity of computers for use in a distributed failure simulation, and is allocated to each computer. SOLUTION: A failure simulation in a plurality of circuit data is executed to prepare a data base 10. In a logic circuit as a target of a distributed failure simulation, a failure list 11 enumerating failures to be assumed is prepared. Next, the failure list 11 is divided based on failure simulation performance data of each computer included in the data base 10, and division failure lists 12a to 12c equal to the number of sets of usable computers are prepared to obtain failure simulation results lists 13a to 13c by a distribution processing. Finally, the obtained results lists are merged to prepare a failure simulation results list 14 of the entire logic circuit to be targeted to output it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a distributed fault simulation method for performing a fault simulation by distributed processing using a plurality of computers.

[0002]

2. Description of the Related Art In order to verify the fault detection ability of test data used to determine whether a logic circuit such as an integrated circuit is good or bad,
A failure simulation is performed to simulate a logic operation when a failure is assumed in a logic circuit and to determine whether given test data can detect the assumed failure. Since the number of faults to be assumed has become enormous with the increase in circuit integration, a fault list listing faults to be simulated is divided into multiple fault lists, and distributed processing is performed using multiple computers. A distributed failure simulation for performing a failure simulation is performed. FIG. 6 is an explanatory diagram schematically showing the procedure and contents of a conventional distributed fault simulation method.

In the conventional distributed fault simulation method shown in FIG. 6, a fault list listing faults for which a fault simulation is performed is created, and the fault list is created according to the number of a plurality of available computers or one computer at a time. The fault list is divided equally for each number of faults that can be processed by
The failure simulation is performed by distributing the equally divided failure lists in each computer.

First, a failure list 61 listing failures to be assumed in a logic circuit to be subjected to a failure simulation is created (step S61). Next, the failure list is divided equally into a plurality of divided failure lists 62a, 62b, and 6 according to the number of available computers or the number of failures that one computer can handle in one process.
2c is created (step S62).

[0005] The divided fault lists 62a, 62b,
Each of the divided failure lists 62a, 62b, and 62c is executed by distributed processing by allocating 62c to an available computer, and failure simulation result lists 63a, 63b, and 63c are obtained (step S63).

Finally, the failure simulation result lists 63a, 63b, 63c are merged to create and output a failure simulation result list 64 for the entire target logic circuit (step S64). That is, a list of detected faults and undetected faults included in each of the fault simulation result lists 63a, 63b, 63c is put together to create a list of all detected faults and undetected faults, and output as the fault simulation result list 64. .

FIG. 7 is a table showing an example of equal division of a fault list in the conventional distributed fault simulation method. This example shows a case where the total number of failures is 10,000.

When the number of available computers is five, the failure list is equally divided according to the number of computers, and the divided failure lists P1, P2, P3 divided into five equal parts
The number of faults included in P4 and P5 is 2000 each.

When only three computers can be used and the maximum number of faults that can be processed by one computer in one process is 2000, the fault list is equally divided every 2000 faults. Then, the failure list is divided into five equal parts, and the divided failure lists P1, P2, P3, P
4, P5.

[0010]

In the above-described conventional distributed fault simulation method, if the processing performance of a plurality of available computers is almost the same, the failure of each computer by the distributed processing of the equally divided fault list is performed. The simulation execution time is almost the same. However, when the processing performance of a plurality of available computers is different, the failure simulation execution time of each computer due to the distributed processing of the equally divided failure list will vary.

FIG. 8 is a graph showing the relationship between the processing performance of the computer and the execution time of the failure simulation.

As shown in the graph of FIG. 8, the failure list is divided into n divided failure lists, and the failure simulation processes P1, P2, P3, P
4,. . . , Pn are respectively assigned to a plurality of computers having different processing performances, the process of the failure simulation assigned to the computer with the higher processing speed ends quickly, and the process of the failure simulation assigned to the computer with the lower processing speed is slower. As a result, the failure simulation execution time of each computer varies.

Therefore, there is a problem that the execution time of the slowest failure simulation process becomes the execution time of the entire failure simulation, and as a result, the turn-around time of the entire failure simulation becomes longer.

Another problem is that the conventional distributed fault simulation method does not consider the optimal and sufficient number of computers necessary for distributed processing of the fault simulation.

FIG. 9 is a graph showing the relationship between the number of computers used and the execution time of the distributed fault simulation.

As shown in the graph of FIG.
That is, as the number of computers used for distributed processing is increased, the execution time of the distributed fault simulation is reduced. However, when the number of computers exceeds a certain number, even if the number of computers is further increased, the distributed fault simulation is not performed. Execution time will not be reduced.

The reason is as follows. In distributed fault simulation, each computer simulates the operation of a logic circuit without a fault and the operation of a logic circuit assumed to have a fault, and compares the results.However, how many fault simulations are distributed However, each computer must always perform an operation simulation of a logic circuit having no failure, and the time cannot be reduced. Also,
The execution time of the operation simulation of the logic circuit in which a fault is assumed is reduced as the number of faults included in the split fault list decreases, but in actuality, the time taken for the processing start operation and the processing end operation of the computer also becomes a failure simulation. Therefore, even if the number of faults included in the split fault list is reduced to a certain degree or more, the execution time of the operation simulation of the logic circuit in which the fault is assumed hardly decreases.

Therefore, as described above, even if the number of computers is increased to a certain extent or more, the execution time of the distributed fault simulation is not shortened. That is, there is an optimal number of computers for executing the distributed fault simulation in a sufficiently short time.

Although the optimum number varies depending on the circuit scale and the like, in the conventional distributed fault simulation method, although the number of available computers is sufficient and the fault simulation can be performed with higher throughput, However, the throughput of the failure simulation is reduced because the processing is performed on a smaller number of computers than the optimal number, and conversely, even though the throughput cannot be increased, the number of computers is larger than the optimal number. There is a problem in that the processing results in wasteful use of computer resources that could otherwise be used for other processing.

The performance of the computer used in the failure simulation at this time varies, but the performance of the computer used has not been taken into consideration in the past, so that the most suitable computer for the distributed processing of the failure simulation is selected. However, there is a problem that a computer with insufficient performance or excessive performance is selected, resulting in a waste of computer resources.

Furthermore, in the conventional distributed fault simulation method, the number of faults that can be processed by one computer in one continuous fault simulation,
There is a problem that the execution time of the distributed fault simulation becomes long because the so-called Fault Per Pass is not taken into account and its value is not appropriate. In other words, the fault-per-path has an optimal value according to the circuit scale for each computer, and if a value smaller than the optimal value is set, the number of times of failure simulation increases and the total execution time becomes longer. If a value larger than the optimum value is set, it exceeds the memory capacity of the computer and the so-called swap operation of the computer occurs frequently, so that the total execution time becomes longer. Therefore, even if the set value of the fault-per-path is too small or too large, the execution time of the fault simulation becomes long.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a distributed fault simulation method capable of performing a distributed fault simulation with high efficiency.

[0023]

According to the distributed fault simulation method according to the first configuration of the present invention, a fault simulated by numerically examining the fault simulation processing capabilities of a plurality of computers to be used for the distributed fault simulation. A first step of creating a database of simulation performance data and a failure list listing failures to be assumed in the logic circuit to be subjected to the distributed failure simulation; and a failure simulation processing capability of each computer based on the failure simulation performance data. A second process of allocating a divided fault list obtained by dividing the fault list to each computer according to the following, and a third process of executing a failure simulation of each divided fault list by distributed processing using each computer. Is characterized by With this configuration, a computer with low performance processes a simulation with a relatively small number of faults, and a computer with high performance processes a simulation with a relatively large number of faults. Therefore, the execution time of the entire failure simulation can be shortened.

The division of the failure list is preferably performed so that the number of failures included in each divided failure list is proportional to the value of the failure simulation performance data of each computer.

According to the distributed fault simulation method according to the second configuration of the present invention, the number of computers required for the distributed fault simulation is checked for each circuit scale, and a database of the required computer number data for each circuit scale is created. The optimum number of computers according to the circuit size of the logic circuit is calculated based on the process 1, the database of the required number of computers for each circuit size, and the circuit connection information of the logic circuit to be subjected to the distributed fault simulation. A second step, and a third step of executing a failure simulation by distributed processing using the calculated optimal number of computers,
With this configuration, it is possible to effectively use computer resources without using an unnecessary number of computers.

According to the distributed fault simulation method according to the third configuration of the present invention, the fault simulation performance obtained by examining the fault simulation processing capabilities of a plurality of computers to be used for the distributed fault simulation for each circuit scale and quantifying the same. First, a database of the total number of required fault simulation performance data obtained by examining the total number of fault simulation performance data obtained by digitizing the data and the fault simulation processing capacity of the computer required for the distributed fault simulation for each circuit scale is created. And a database of the failure simulation performance data of each computer for each circuit scale and the data of the total number of required failure simulation performances,
A second step of calculating an optimum total number of fault simulation performances of the computer according to the circuit scale of the logic circuit based on the circuit connection information of the logic circuit to be subjected to the distributed fault simulation; And a fourth step of executing a failure simulation by distributed processing using the selected computers by selecting a required number of optimum computers from the respective computers. According to this configuration, the execution time of the distributed fault simulation can be shortened by effectively using the computer resources without using more computers than necessary and the number of computers.

According to the distributed fault simulation method according to the fourth configuration of the present invention, at any point before the fourth step in the third configuration of the present invention, a plurality of faults to be used for the distributed fault simulation are obtained. Fault-per-unit, which is the number of faults that each of the three computers can handle in one continuous fault simulation
The fifth step of examining the optimum value of the path for each circuit scale and creating a database of fault-per-path data of each computer for each circuit scale, and the third step of the present invention.
After the third process and before the fourth process in the configuration of the above, based on a database of fault-per-path data of each computer for each circuit size and circuit connection information of a logic circuit to be subjected to the distributed fault simulation, Calculating an optimum value of the fault-per-path of each computer selected in the third step according to the circuit size of the logic circuit;
A sixth step of setting an optimum value of a fault-per-path for each computer, whereby the computer resources can be effectively used without using more computers and computers than necessary. Thus, the execution time of the distributed fault simulation can be reduced to a minimum.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a distributed fault simulation method according to the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory diagram schematically showing the procedure and contents of the distributed fault simulation method according to the first embodiment of the present invention.

In the distributed fault simulation method according to the first embodiment of the present invention shown in FIG. 1, first, a plurality of computers to be used in the distributed fault simulation perform a fault simulation on a plurality of circuit data. Then, the failure simulation processing capability of each computer is checked, and the result is quantified as failure simulation performance data of each computer, and a database 10 of failure simulation performance data is created (step S10).

On the other hand, a fault list 11 listing faults to be assumed in the logic circuit to be subjected to the distributed fault simulation is created (step S11). Note that the order of step S10 and step S11 is not specified.

Next, the failure list 11 is divided based on the failure simulation performance data of each computer included in the database 10, and a plurality of divided failure lists 12a, 12 equal to the number of available computers are divided.
b and 12c are created (step S12). More specifically, the failure list 11 is divided into divided failure lists 12a, 12b, and 12 so that the number of failures is proportional to the numerical value of the failure simulation performance data of each computer.
Create c.

Then, the split fault lists 12a, 12b,
12c is assigned to each computer corresponding to the failure simulation performance data, and each divided failure list 1
The failure simulations 2a, 12b, and 12c are executed by distributed processing to obtain failure simulation result lists 13a, 13b, and 13c, respectively (step S1).
3).

Finally, the failure simulation result lists 13a, 13b, and 13c are merged to create and output a failure simulation result list 14 for the entire target logic circuit (step S14). That is, a list of detected faults and undetected faults included in each of the fault simulation result lists 13a, 13b, and 13c is compiled to create a list of all detected faults and undetected faults, and is output as the fault simulation result list 14. .

As described above, in the distributed fault simulation method according to the first embodiment of the present invention, the fault list is divided on the basis of the performance of each computer. Computers with a small number of faults are to be simulated, while computers with high performance are to be simulated with a relatively large number of faults, so that the distributed fault simulation execution time by a plurality of computers is equalized and the execution time variation is reduced. be able to. As a result, the execution time of the entire failure simulation, that is, the turnaround time of the entire failure simulation can be reduced.

FIG. 2 is a diagram showing computer-based fault simulation performance data (FIG. 2) quantified in the distributed fault simulation method according to the first embodiment of the present invention.
2A is a table showing an example of the number of faults (FIG. 2B) included in a split fault list that is split so that the number of faults is proportional to the value of the fault simulation performance data.

In the example shown in FIG. 2A, five computers C1, C2, C3, C4 and C5 can be used.
The case where the numerical value of the failure simulation performance data of each computer is 5, 12, 6, 8, 9 is shown.

In this case, when the total number of faults to be subjected to the fault simulation is 10,000, the number of 10,000 faults is set so that the number of faults is proportional to the values 5, 12, 6, 8, and 9 of the fault simulation performance data. When divided, 1250, 3000, 1500, 2000
And 2250. Therefore, as shown in FIG. 2B, the divided fault lists P1, P2, P3, P4, P4 assigned to the computers C1, C2, C3, C4, C5
The number of faults included in 5 is 1250, 3000, 150
0, 2000, and 2250.

FIG. 3 is an explanatory diagram schematically showing the procedure and contents of the distributed fault simulation method according to the second embodiment of the present invention.

As described above, in the distributed fault simulation, when the number of computers used for distributed processing exceeds the number of computers, the execution time of the distributed fault simulation cannot be shortened even if the number of computers is further increased. Yes, there is an optimal number of computers for distributed fault simulation.

Therefore, in the distributed fault simulation method according to the second embodiment of the present invention shown in FIG. 3, first, a plurality of computers to be used in the distributed fault simulation execute a fault for a plurality of circuit data. The simulation is executed, the number of computers required for the distributed fault simulation is checked for each circuit size, and the required number of computers data for each circuit size obtained as a result is collected. Is created (step S31). Specifically, the data collection and the creation of the database 31 are performed by checking the relationship between the number of computers used and the execution time of the distributed fault simulation shown in FIG. 9 for each circuit size. That is, the number of computers used for distributed processing is changed, and the execution time of each computer is checked.

Next, based on the database 31 of the required number of computers for each circuit size and the circuit connection information 30 of the logic circuit to be subjected to the distributed fault simulation, the most suitable computer corresponding to the circuit size of the logic circuit is obtained. The number is calculated (step S32).

Then, a failure simulation by distributed processing is executed using the calculated number of computers (step S33). As a result, it is possible to avoid the irrationality that the execution time cannot be shortened even if the distributed fault simulation is performed using more computers than necessary, and to effectively use the computer resources without wasting them.

FIG. 4 is an explanatory diagram schematically showing the procedure and contents of the distributed fault simulation method according to the third embodiment of the present invention.

In the distributed fault simulation method according to the third embodiment of the present invention shown in FIG. 4, fault simulation performance data is collected for each circuit scale for a plurality of computers to be used for distributed fault simulation. . That is, even in the same computer, the processing speed varies depending on the circuit scale of the logic circuit to be subjected to the failure simulation. Therefore, the failure simulation performance data of each computer shown in FIG. Then, a database 41 of failure simulation performance data of each computer is created for each circuit size (step S41). The data in the database 41 may include the necessary computer number data for each circuit size in the second embodiment of the present invention. However, in the third embodiment of the present invention,
Failure simulation performance that quantifies the failure simulation processing capacity of a computer in order to clearly understand how many computers and how many computers are required for distributed failure simulation, rather than simply calculating the number of computers required As the total number of data, the necessary failure simulation performance total number data for each circuit scale is calculated and collected.

Next, a database 41 of failure simulation performance data of each computer for each circuit size,
Based on the circuit connection information 40 of the logic circuit to be subjected to the distributed fault simulation, the optimum total number of the fault simulation performances of the computer according to the circuit scale of the logic circuit is calculated, and the calculated total number of the fault simulation performances is obtained. Then, the optimum number of computers are selected from the available computers (step S4).
2).

Then, a failure simulation by distributed processing is executed using the selected optimum computer (step S43). As a result, the execution time of the distributed fault simulation can be shortened by effectively using the computer resources without using more computers and computers than necessary.

FIG. 5 is an explanatory diagram schematically showing the procedure and contents of the distributed fault simulation method according to the fourth embodiment of the present invention.

As described above, in the conventional distributed fault simulation method, the number of faults that can be processed by one computer in one continuous fault simulation, so-called Fault Per Path (Fault Per Path)
Since the value of (Pass) is not set appropriately, there is a problem that the execution time of the distributed fault simulation becomes long.

Therefore, in the distributed fault simulation method according to the fourth embodiment of the present invention, in addition to the configuration of the third embodiment of the present invention, each computer to be used for the distributed fault simulation is further provided. The fault per path, which is the number of faults that can be processed by one continuous fault simulation, is also examined for each circuit size, and a database of fault per path data of each computer for each circuit size is obtained. 51 is created (step S51). On the other hand, as in the configuration of the third embodiment of the present invention, the necessary number of optimal computers are selected from the available computers so that the required total number of fault simulation performances can be obtained.

Next, a database 51 of fault-per-pass data of each computer for each circuit size,
Based on the circuit connection information 50 of the logic circuit to be subjected to the distributed fault simulation, the optimum value of the fault-per-path according to the circuit size of each selected computer is calculated (step S52).

Then, a fault simulation by distributed processing is executed using the selected optimum computer and setting the calculated optimum value of the fault-per-path (step S53). As a result, the execution time of the distributed fault simulation can be shortened to a minimum by using computer resources effectively without using computers with more performance and number than necessary.

[0053]

According to the distributed fault simulation method according to the first configuration of the present invention, the divided fault list obtained by dividing the fault list according to the fault simulation processing capabilities of a plurality of computers to be used for the distributed fault simulation is obtained. Computers with low performance will perform simulations with a relatively small number of failures, and computers with high performance will perform simulations with a relatively large number of failures. The failure simulation execution time can be equalized, and the variation in the execution time can be reduced. As a result, the execution time of the entire failure simulation, that is, the turnaround time of the entire failure simulation can be reduced.

According to the distributed fault simulation method according to the second configuration of the present invention, the number of computers required for the distributed fault simulation is checked for each circuit scale, and a database of the required computer number data for each circuit scale is created. Since the optimal number of computers according to the circuit size of the logic circuit to be subjected to the distributed fault simulation is calculated, computer resources can be effectively used without using an unnecessary number of computers. .

According to the distributed fault simulation method according to the third configuration of the present invention, the fault simulation performance obtained by numerically examining the fault simulation processing capabilities of a plurality of computers to be used in the distributed fault simulation for each circuit scale. Data and the total number of failure simulation performance data obtained by quantifying the failure simulation processing capacity of the computer required for the distributed failure simulation are created for each circuit scale, and a database of the required total number of failure simulation performance data is created. Calculate the optimum total number of fault simulation performances of the computers according to the circuit scale of the logic circuit to be subjected to the distributed fault simulation, and select the optimum number of computers from each computer so that the total number of fault simulation performances can be obtained Since it was decided to select only the required number of computers, without using undue performance and many computers, it is possible to effectively utilize computer resources, to reduce the execution time of the distributed fault simulation.

According to the distributed fault simulation method according to the fourth configuration of the present invention, in the above-described third configuration of the present invention, each of the plurality of computers to be used for the distributed fault simulation includes one continuous operation. The optimum value of the fault-per-path, which is the number of faults that can be processed by the fault simulation, is checked for each circuit size, and the fault value of each computer for each circuit size is determined.
Create a database of purpose-pass data, calculate the optimal value of the fault-purpose path according to the circuit size of each selected computer according to the circuit size of the logic circuit to be subjected to the distributed fault simulation, and Since the optimal value of the fault-per-path is set for the computer, the execution time of the distributed fault simulation is minimized by effectively using the computer resources without using more computers and computers than necessary. Can be shortened.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram schematically showing a procedure and contents of a distributed fault simulation method according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating computer-based failure simulation performance data (FIG. 2A) and the number of failures proportional to the failure simulation performance data quantified in the distributed failure simulation method according to the first embodiment of the present invention. Table showing an example of the number of faults (FIG. 2 (b)) included in the split fault list thus split.

FIG. 3 is an explanatory view schematically showing procedures and contents of a distributed fault simulation method according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram schematically showing a procedure and contents of a distributed fault simulation method according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram schematically showing a procedure and contents of a distributed fault simulation method according to a fourth embodiment of the present invention.

FIG. 6 is an explanatory view schematically showing a procedure and contents of a conventional distributed fault simulation method.

FIG. 7 is a table showing an example of equal division of a fault list in a conventional distributed fault simulation method.

FIG. 8 is a graph showing the relationship between the processing performance of a computer and the failure simulation execution time.

FIG. 9 is a graph showing the relationship between the number of computers used and the execution time of the distributed fault simulation.

[Explanation of symbols]

10 Database of fault simulation performance data 11 Fault list 12a, 12b, 12c Split fault list 13a, 13b, 13c Fault simulation result list 14 Overall fault simulation result list 30, 40, 50 Circuit connection of logic circuits to be subjected to fault simulation Information 31 Database of the required number of computers for each circuit size 41 Fault simulation performance database of each computer for each circuit size 51 Database of fault-per-path for each computer for each circuit size 61 Failure list 62a, 62b, 62c Split failure list 63a , 63b, 63c Failure simulation result list 64 Overall failure simulation result list

Claims (5)

[Claims] 1. A database of fault simulation performance data quantified by examining fault simulation processing capabilities of a plurality of computers to be used for distributed fault simulation and a logical circuit to be subjected to distributed fault simulation. A first step of creating a failure list listing the failures; and assigning a divided failure list obtained by dividing the failure list to each of the computers according to the failure simulation processing capability of each of the computers based on the failure simulation performance data. A second step of performing a failure simulation of each of the divided failure lists by distributed processing using the computers;
A distributed failure simulation method, comprising: 2. The method according to claim 1, wherein the division of the failure list is performed such that the number of failures included in each of the divided failure lists is proportional to a value of the failure simulation performance data of each of the computers. The distributed failure simulation method described in the above. 3. A first step of examining the number of computers required for distributed fault simulation for each circuit scale and creating a database of required computer number data for each circuit size; A second calculating step of calculating the optimal number of computers according to the circuit scale of the logic circuit based on the database and the circuit connection information of the logic circuit to be subjected to the distributed fault simulation;
And a third step of executing a failure simulation by distributed processing using the calculated optimal number of computers. 4. Fault simulation performance data obtained by numerically examining fault simulation processing capabilities of a plurality of computers to be used for distributed fault simulation for each circuit size, and computer fault simulation processing required for distributed fault simulation A first step of examining the total number of fault simulation performance data in which the capability is quantified for each circuit scale and creating a database of the required total number of required failure simulation performance data, and the fault simulation of each computer for each circuit scale; An optimal computer corresponding to the circuit scale of the logic circuit based on the database of the performance data and the data of the total number of required failure simulation performances and the circuit connection information of the logic circuit to be subjected to the distributed failure simulation. A second step of calculating the total number of failure simulation performances of the computer, and a third step of selecting only the required number of optimum computers from among the computers so as to obtain the calculated total number of failure simulation performances. A fourth step of executing a failure simulation by distributed processing using each of the computers described above. 5. A fault which is the number of faults which can be processed in one continuous fault simulation by each of a plurality of computers to be used in a distributed fault simulation at any time before the fourth step. The optimum value of the par pass is checked for each circuit size, and the fault per
A fifth step of creating a path data database; after the third step and before the fourth step, a database of the fault-per-path data of each computer for each circuit size; Based on the circuit connection information of the logic circuit to be simulated, based on the circuit size of the logic circuit, calculate an optimal value of the fault-per-path of each of the computers selected in the third step, The method according to claim 4, further comprising: setting a fault-per-path optimum value for each computer.