JP2000048596A - Test apparatus, relief simulation method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To faithfully recreate an actual relief determination and perform a yield prediction with high precision. SOLUTION: A fail bit map and relief condition data stored in a data storing section 10 are retrieved into a fail memory 14, and a memory repair analyzer 13 performs relief simulation based on these fail bit map data and relief condition data to faithfully recreate an actual relief determination. From this relief simulation, yield prediction is performed with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rescue simulation technique, and more particularly, to an inspection apparatus capable of highly accurately predicting a yield in relieving a memory line.
The present invention relates to a relief simulation method and a technique effective when applied to a storage medium.

[0002]

2. Description of the Related Art According to studies made by the present inventor, D
In the case of performing a relief simulation such as yield prediction in a semiconductor integrated circuit device such as a RAM, a simple calculation based on a Poisson distribution, which is one of discrete probability distributions, a point defect (one-bit defect), and the like has been obtained.

[0003] As an example describing this kind of relief simulation in detail, see May 25, 1985.
Published by The Industrial Research Institute, Inc., Kazuo Maeda (Author), “Latest LSI Process Technology” P516-P524, and this document describes yield simulation in semiconductor device manufacturing.

[0004]

However, it has been found by the present inventors that the above-described rescue simulation technique has the following problems.

That is, in a rescue simulation based on a simple calculation of a Poisson distribution, a point defect, or the like, the simulation result merely indicates the rescue efficiency in a fictitious model, and is far from an actual defect. There is a problem that it cannot be determined.

Further, there is another problem that the absolute value of the yield with respect to the actual relief simulation is not known, and the design depends on the experience of the designer.

An object of the present invention is to provide an inspection apparatus, a relief simulation method, and a storage medium capable of faithfully reproducing an actual relief judgment and performing highly accurate yield prediction.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In other words, the inspection apparatus of the present invention stores storage means for storing fail bitmap data and rescue condition data, and performs a rescue simulation based on the fail bitmap data and rescue condition data stored in the storage means. And rescue simulation means for calculating rescue result data.

Further, the inspection apparatus of the present invention is provided with arithmetic means for predicting the yield based on the relief result data simulated by the relief simulating means.

Further, in the inspection apparatus according to the present invention, the relief simulating means counts the number of fail bits from the fail bit map data stored in the storage means, and the number of fail bits can be reduced based on the repair condition data. And a first determination processing unit for reducing the fail bitmap data based on the spare line size when it is determined that the repair is possible, and reducing the size of the fail bit map data to the spare line size by the first determination processing unit. The contracted fail bit map data is subjected to contraction processing by designating contraction in the local bank, the number of fail bits in the contracted local bank is counted, and the number of fail bits counted and the relief limit are counted. A second determination processing unit that compares the number of fail bits with each other and determines whether or not rescue is possible; If the judgment processing unit judges that rescue is possible, the priority remedy judgment processing unit that performs the defect remedy processing of the row line and the column line based on the rescue condition data and the number of remedy sets between the respective local banks have been exceeded. And a third determination processing unit for determining whether or not the number of relief sets in the global bank has exceeded the number of relief sets based on the relief condition data.

The repair simulation method of the present invention counts the number of fail bits from the fail bit map data, and determines whether the number of fail bits can be remedied based on rescue condition data stored in advance. A step of reducing the fail bitmap data to the spare line size when it is determined that the repair is possible in the determination step, and specifying a contraction in the local bank of the fail bitmap data reduced to the spare line size And the number of fail bits of the reduced local bank are counted, and the number of failed bits counted is compared with the number of fail bits at the repair limit to determine whether repair is possible. Process and
If the repair is possible, the process of repairing the defective row and column lines in all the local and global banks according to the priority of the repair condition data, and whether the number of repair sets between the local banks is not exceeded Is determined based on the rescue condition data,
If the number exceeds the number of repair sets in the local bank, and if the number of repair sets does not exceed the number of repair sets between the local banks, whether the number of repair sets in the global bank does not exceed based on the repair condition data Judge,
If the number exceeds the limit, a step of ending the defect rescue process is provided.

Further, the recording medium of the present invention counts the number of fail bits from the fail bit map data, and determines whether the number of fail bits can be remedied based on rescue condition data stored in advance, A step of reducing the fail bitmap data to the spare line size when it is determined that the repair is possible in the determination step; and specifying the contraction in the local bank of the fail bitmap data reduced to the spare line size. A step of reducing the number of fail bits of the reduced local bank and a step of comparing the counted number of fail bits with the number of fail bits at the rescue limit to determine whether rescue is possible If the repair is possible, repair the defective row and column lines The process to be performed in all local banks and global banks based on the priority order, and whether or not the number of relief sets between the respective local banks is exceeded based on the rescue condition data. The step of terminating the defect remedy process and, if the number of repair sets among the local banks does not exceed the number of repair sets in the global bank based on the repair condition data, In this case, the program for executing the step of terminating the defect rescue processing when the program is executed is recorded.

As described above, since the actual rescue judgment can be faithfully reproduced, the yield can be predicted with high accuracy, and efficient and effective line rescue can be performed.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory test system according to one embodiment of the present invention. FIG. 2 is an explanatory diagram of repair result data processing in a relief simulation of the memory test system according to one embodiment of the present invention. FIG. 3 is an explanatory diagram of the input data processing in the relief simulation of the memory test system according to the embodiment of the present invention. FIGS. 4 and 5 are flowcharts of the relief simulation in the memory test system according to the embodiment of the present invention. FIG. 6 is an explanatory diagram of repair condition data used in the memory test system according to one embodiment of the present invention, and FIG.
8 is an explanatory diagram of a bitmap used in the memory test system according to the embodiment of the present invention, FIG. 8B is an explanatory diagram of a local bank size in the bitmap, and FIG.
FIG. 3 is an explanatory diagram of work data used in the memory test system according to one embodiment of the present invention.

In the present embodiment, a memory test system (inspection apparatus) 1 performs a relief simulation in a semiconductor integrated circuit device such as a DRAM. The memory test system 1 includes a memory tester 2 as shown in FIG. The memory tester 2 controls all hardware and software controls in a memory test.

The memory tester 2 is provided with a test head 3. The test head 3 is connected to a voltage supply unit 4, a program power supply 5, and a DC test unit 6. The device under test (memory device) 7 which is a semiconductor integrated circuit device such as a DRAM to be tested is directly mounted on the test head 3.

The voltage supply unit 4 and the program power supply 5 supply power to the test head 3, the semiconductor integrated circuit device, and the like. The DC test unit 6 evaluates DC characteristics such as input / output current, input / output voltage, and power supply of the semiconductor integrated circuit device.

As shown in FIG. 2, the memory tester 2 uses the fail bit map and the rescue condition data to
The rescue result and the yield prediction are calculated. The fail bit map is a map illustrated so that the position (address) of a defective cell detected in a probe test or the like can be visually confirmed.

A computer 8 such as a work station or a personal computer is connected to the memory tester 2 by a tester bus 9. Computer 8
A storage unit (storage medium) 8a, such as a hard disk, provided in the computer 8 for inputting / outputting various data and displaying data, stores a relief simulation program for performing a relief simulation. The operation of the memory tester 2 is controlled by inputting a command from the computer 8, and the memory tester 2 is controlled via the tester bus 9.
The input and output of data between the computer and the computer 8 are performed.

A data storage unit 10 such as a hard disk or a cartridge magnet tape is connected to the computer 8. The computer 8 has a LAN
(Local Area Network) or the like, and is connected to another computer or the like.

Also, as shown in FIG.
The inspection result such as the probe inspection performed by the computer 8 is input to the computer 8, and the computer 8 calculates the data of the fail bit map. Here, the fail bitmap data may be fail bitmap data generated from a Monte Carlo simulation or the like based on a failure prediction instead of the fail bitmap data generated from an actual inspection result.

The internal configuration of the memory tester 2 will be described.

In the memory tester 2, as shown in FIG.
A tester processor 12 is provided. The tester processor 12 controls all the controls of the memory tester 2. The tester processor 12 includes a memory repair analyzer (rescue simulation means, calculation means, first to third judgment processing units) 13, a fail memory (storage means) 1.
4 and algorithm pattern generator 15
Are connected via the internal bus 9a.

The memory repair analyzer 13 analyzes the input data and determines the rescue. Fail memory 14
Stores various data such as fail bitmap data and rescue condition data output from the computer 8 or the like. The algorithm pattern generator 15 generates various pattern signals for evaluating a device under test.

The fail memory 14 is connected to a memory repair analyzer 13 and an algorithm pattern generator 15. The algorithm pattern generator 15 includes a programmable data selector 16
The programmable data selector 16 converts a pattern signal output from the algorithm pattern generator 15 into a format controller 17.
Alternatively, the output is switched to one of the sense controls 18.

The programmable data selector 16 includes:
The format controller 17 and the sense control 18 are connected. Format controller 1
7 combines the pattern signal output from the algorithm pattern generator 15 and the timing of the timing generator 19 to generate a test signal to be applied to the device under test. The sense control 18 converts an analog signal such as a voltage output from the device under test into a digital signal.

Further, a timing generator 19 is connected to the fail memory 14, the algorithm pattern generator 15, the format controller 17 and the sense control 18, and the timing generator 19 generates a timing signal at a predetermined timing.

Further, a variable delay 20 is connected to the format control 17. The variable delay 20 adjusts the timing of the test signal output from the format control 17. The test head 3 described above is connected to the sense control 18 and the variable delay 20.

Next, the operation of the present embodiment will be described with reference to FIG.
3, 4, 5, an example of the rescue condition data of FIG. 6, an explanatory diagram of the bit map of FIG.
This will be described using an example of the work data.

First, the data of the aforementioned fail bit map is inputted from the computer 8 and stored in the fail memory 14 of the memory tester 2 (step S101).
The memory repair analyzer 13 counts the number of fail bits based on the fail bit map data stored in the fail memory 14 (Step S102).

The memory repair analyzer 13 determines whether or not the number of fail bits can be repaired based on the repair condition data stored in the fail memory 14 in advance (step S103).

FIG. 6 shows a memory repair analyzer 1.
7 shows an example of the rescue condition data stored in FIG.
(A) and (b) are explanatory diagrams of a bitmap. FIG.
(A) shows the spare line size of the row line spare and the column line spare.

FIG. 7B shows the local bank size, which is obtained by dividing the memory space in the device under test 7 into a certain size.

Further, one or two or more local banks are gathered to form a global bank size, and relief is performed for each local bank and global bank. In the present embodiment, since the local bank size and the global bank size are the same, the number of local banks and the number of global banks are the same.

If it is determined in step S103 that the repair is possible, the memory repair analyzer 13 reduces the fail bitmap data according to the spare line size (step S104). If it is determined that the rescue is impossible, the rescue simulation ends.

Then, the memory repair analyzer 13
Reduction processing is performed on the fail bitmap data that has been reduced to the spare line size by designating reduction in the local bank (step S105).

After that, the memory repair analyzer 13
Based on the reduced fail bitmap data, work data in the local bank is created as shown in FIG. 8 (step S106).

The memory repair analyzer 13 counts the number of fail bits in the local bank (step S107), compares the counted number of fail bits with the number of fail bits at the repair limit, and determines whether repair is possible. Is performed (step S108).

If it is determined in step S108 that the repair can be performed, the memory repair analyzer 13 determines whether the repair is low-line priority or column-line priority based on the repair condition data (step S10).
9). If it is determined in step S108 that the rescue is impossible, the rescue simulation ends.

In the processing of step S109, if it is determined that the priority is given to the row line, the row line defect repair processing is performed (step S110), and then the column line defect repair processing is performed (step S111).

Further, in the process of step S109,
If it is determined that the priority is given to the column line, the defect repair process for the column line is performed (step S112), and then the defect repair process for the row line is performed (step S113).

After performing any one of steps S110 and S111 or steps S112 and S113, the memory repair analyzer 13 determines whether or not the number of repair sets (the number of spare lines) has been exceeded (step S110).
114).

In the process of step S114, when the number of fail bits does not exceed the rescue set, it is determined whether the number of fail bits is 0 or 1 or more (step S115). The simulation ends.

If the number of fail bits is 0 in the processing of step S115, the processing of another local bank is performed, and the processing of all the local banks is performed by repeating the processing of steps S106 to S115.

If the number of fail bits is one or more, the memory repair analyzer 13 determines from the repair condition data whether the repair is row line priority or column line priority (step S116).

In the process of step S116, if it is determined that the priority is on the row line, the defect repair process of the row line is performed (step S117), and then the defect repair process of the column line is performed (step S118).

In the process of step S116,
If it is determined that the priority is given to the column line, the defect repair process for the column line is performed (step S119), and then the defect repair process for the row line is performed (step S120).

After performing any one of steps S117 and S118 or steps S119 and S120, the memory repair analyzer 13 counts the number of fail bits and determines whether the number is 0 or 1 or more (step S117). S121).

In the process of step S121, when the fail bit count is 0, the memory repair analyzer 13 determines whether or not the number exceeds the repair set (step S122).

If the number of repair sets has not exceeded, the memory repair analyzer 13 determines whether all local bank processes have been completed (step S1).
23) If completed, it is determined based on the rescue condition data whether the number of rescue sets between the local banks has not been exceeded (step S124).

If the number exceeds the number of relief sets, the relief simulation ends. Step S123
If the local bank process has not been completed in the process of (1), the process returns to step S106.

If the number of repair sets between the local banks does not exceed the number of repair sets in step S124, the memory repair analyzer 13 determines whether or not the processing in the global bank has been completed (step S125). If the processing has been completed, the memory repair analyzer 13 determines whether or not the number of repair sets in the global bank has been exceeded based on the repair condition data (step S126). Further, in the processing of steps S121, S122, S124, and S126, if the number of the rescue sets is exceeded, the rescue simulation ends.

Then, based on the relief simulation faithfully reproducing the actual relief, the memory repair analyzer 1
3 performs yield prediction and the like, and outputs the result to the computer 8 or the like.

Thus, in the first embodiment, the repair simulation can be performed using the fail bit map data, which is the actual inspection result, by the memory repair analyzer 13 provided in the memory test system 1, so that the actual repair determination is made. It is possible to faithfully reproduce and perform highly accurate yield prediction and efficient and effective line relief.

Also, in the present embodiment, the memory test system 1 for performing a relief simulation in line relief has been described. For example, random bit relief or ECC (Erro
Even if another repair simulation such as (r CorrectingCode) determination is performed, highly accurate yield prediction can be performed.

In this ECC processing, for example, Ha
SEC-DED (Singl
e Error Correct-Double Er
In the case of a (72, 64) code that is (ror detect), if the error in the read 72 bits is 1 bit, the error can be corrected, and if the error is 2 bits, the error can be detected. Therefore,
Error correction becomes possible with a probability of 1/72.

When performing ECC processing, the necessary parameters are the definitions of error correction codes (code length, correctable bits, etc.).
The location may be defined on the fail bit map after the sign.

Next, the ECC processing will be described with reference to the flowchart of FIG.

Here, the processing of steps S201 to S203 is the same as the processing of steps S101 to S103 in FIG.

If it is determined in step S203 that rescue is possible, the memory repair analyzer 13
(FIG. 1) reads out after one code (step S20).
4), the number of fail bits (bytes) is counted (step S205). If it is determined that the repair cannot be performed, the ECC processing ends.

The memory repair analyzer 13 determines whether or not the number of fail bits is within the correction capability based on the ECC processing condition data shown in FIG. 10 (step S20).
6). If the number of fail bits is larger than the correction capability, the ECC processing ends. Then, when the processing of all codewords is completed, the ECC processing is completed, and
If the processing has not been completed, the processing of steps S204 to S206 is repeated.

In the case where the line relief simulation and the ECC processing in this embodiment are combined, as shown in FIG. 11, the ECC processing may be performed after the line relief simulation is completed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the relief simulation function was added to the memory tester. However, the relief simulation function may be added to a virtual memory tester for creating a test program and debugging the test program.

This virtual memory tester is equipped with a simulation model having the same function as the memory tester of the real device, and can be used from the stage of developing a test program.

Further, all the commands (commands) used for controlling the memory tester can be reflected on the virtual memory tester, and not only the test conditions of the test program but also how the program operates the memory tester is described. Whether to set and control can be verified almost in the same manner as the actual machine. The verified program can be directly developed on an actual memory tester.

Further, according to the above-described embodiment, the memory tester to which the relief simulation function is added has been described. However, the relief test having only the relief simulation function without adding the relief simulation function to the memory tester is described. A simulator may be formed, and the rescue simulator and the memory tester may be connected.

[0071]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by providing the relief simulation means and the calculation means in the inspection apparatus,
Since the actual relief judgment can be faithfully reproduced, highly accurate yield prediction can be performed.

(2) In the present invention, according to the above (1), efficient and effective line repair can be performed, and the cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory test system according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of relief result data processing in relief simulation of the memory test system according to one embodiment of the present invention;

FIG. 3 is an explanatory diagram of input data processing in relief simulation of the memory test system according to the embodiment of the present invention;

FIG. 4 is a flowchart of a relief simulation in the memory test system according to the embodiment of the present invention;

FIG. 5 is a flowchart of a relief simulation in the memory test system showing a continuation of FIG. 4;

FIG. 6 is an explanatory diagram of repair condition data used in the memory test system according to one embodiment of the present invention;

FIG. 7A is an explanatory diagram of a bitmap used in a memory test system according to an embodiment of the present invention;
(B) is an explanatory diagram of a local bank size in a bitmap.

FIG. 8 is an explanatory diagram of work data used in the memory test system according to one embodiment of the present invention.

FIG. 9 is a flowchart of an ECC process in a memory test system according to another embodiment of the present invention.

FIG. 10 is an explanatory diagram of ECC processing data used in a memory test system according to another embodiment of the present invention.

FIG. 11 is a flowchart in a case where repair processing and ECC processing are performed in a memory test system according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Memory test system (inspection apparatus) 2 Memory tester 3 Test head 4 Voltage supply unit 5 Program power supply 6 DC test unit 7 Device under test (memory device) 8 Computer 8a Storage unit (storage medium) 9 Tester bus 9a Internal bus 10 Data Storage unit 11 Circuit 12 Tester processor 13 Memory repair analyzer (rescue simulation means, calculation means, first to third judgment processing units) 14 Fail memory (storage means) 15 Algorithm pattern generator 16 Programmable data selector 17 Format controller 18 Sense Control 19 Timing generator 20 Variable delay

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA07 AB00 AC03 AD00 AE06 AE08 AE09 AE10 AE12 AE14 AG03 AG07 AH07 AK01 AL00 4M106 AA02 AA07 AB07 BA14 CA70 DA14 DG23 DJ38 5L106 DD24 DD25 DD26 EE02

Claims (5)

[Claims] An inspection apparatus for inspecting a memory device, comprising: storage means for storing fail bitmap data and rescue condition data; and fail bitmap data and rescue condition data stored in the storage means. A repair simulation means for performing a relief simulation based on the result and calculating relief result data. 2. The inspection apparatus according to claim 1, further comprising an arithmetic unit for predicting a yield based on the relief result data simulated by the relief simulation unit. 3. The inspection apparatus according to claim 1, wherein the rescue simulation means counts the number of fail bits from the fail bit map data in the storage means, and determines the number of fail bits based on the rescue condition data. A first determination processing unit that determines whether or not rescue is possible, and reduces the fail bitmap data to a spare line size when it is determined that rescue is possible; The fail bit map data subjected to the contraction processing is contracted by designating contraction within the local bank, the number of fail bits in the contracted local bank is counted, and the number of fail bits counted and the relief limit are counted. A second determination processing unit that compares the number of fail bits with When the second judgment processing unit judges that the rescue is possible, a priority remedy judgment processing unit that performs a defect remedy process on the row line and the column line based on the rescue condition data, and the number of rescue sets between the respective local banks And a third judgment processing unit for judging whether or not the number of rescue sets in the global bank does not exceed based on the rescue condition data. 4. A step of counting the number of fail bits from the fail bit map data to determine whether the number of fail bits can be rescued based on rescue condition data stored in advance, and determining whether rescue is possible in the determination step. If determined, a step of reducing the fail bitmap data to the spare line size; and a step of reducing the fail bitmap data reduced to the spare line size by designating a reduction in the local bank. Counting the number of fail bits of the reduced local bank, comparing the counted number of fail bits with the number of fail bits at the rescue limit, and determining whether rescue is possible; In this case, all repairs for defective rows and column lines are A step performed in the local bank and the global bank, and a step of judging whether or not the number of rescue sets between the respective local banks is exceeded based on the rescue condition data, and if the number is exceeded, terminating the defect rescue process If the number of relief sets between the local banks does not exceed the number of relief sets in the global bank, it is determined whether or not the number of relief sets in the global bank has been exceeded based on the relief condition data. And c. Ending the step. 5. A recording medium on which a program for performing a relief simulation based on a fail bit map and rescue condition data is recorded, wherein the number of fail bits is counted from the fail bit map data, and based on the rescue condition data stored in advance. Determining whether the number of fail bits can be remedied, and reducing the fail bit map data to the spare line size when it is determined that rescue is possible in the determining step; A step of reducing the processed fail bit map data by designating reduction in the local bank; and causing the number of fail bits of the reduced local bank to be counted. Compare the numbers to determine if relief is possible. And, if repair is possible, performing a repair of a defective row line and a column line in all local and global banks based on the priority of the repair condition data, and a repair set between the respective local banks. Determining whether or not the number of repair sets does not exceed the number of repair sets based on the repair condition data. A recording medium on which is recorded a program for making a decision as to whether or not the number of relief sets in the global bank is exceeded based on data, and, if so, ending a defect relief process.