JP2006195754A - Circuit operation verification method, circuit operation verification device, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit operation verification method, a circuit operation verification device, and a computer program, capable of correctly and speedily verifying whether or not a circuit element built in a semiconductor integrated circuit malfunctions by considering each voltage drop of power supply wiring and grounding wiring. <P>SOLUTION: Based on a function showing the relation between the total amount of voltage drops and the amount of a delay variation, the amount of an allowable power supply voltage drop ΔV<SB>DDY</SB>and the amount of an allowable grounding voltage drop ΔV<SB>SSY</SB>corresponding to the amount of the delay variation P<SB>Y</SB>which satisfies design constraints are determined, and when the amount of a power supply voltage drop ΔV<SB>DDDC</SB>of the circuit element determined based on mask layout data is smaller than ΔV<SB>DDY</SB>, or the amount of a grounding voltage drop ΔV<SB>SSDC</SB>is smaller than ΔV<SB>SSY</SB>, the circuit element is determined to malfunction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit operation verification method, a circuit operation verification apparatus, and a computer program for verifying the operation of a circuit element included in a semiconductor integrated circuit using a circuit operation verification apparatus.

  For example, in a semiconductor integrated circuit design process using an automatic placement and routing apparatus, the automatic placement and routing apparatus generates mask layout data for a photomask. Then, a semiconductor integrated circuit is manufactured based on the generated mask layout data.

  During operation of the semiconductor integrated circuit, the power supply voltage changes along the power supply wiring path due to the resistance of the power supply wiring. In particular, when a semiconductor integrated circuit is highly integrated, increased in speed, and reduced in voltage, the effect of a voltage drop (hereinafter referred to as a power supply voltage drop) due to power supply wiring becomes large, and the circuit operation speed of the semiconductor integrated circuit decreases. There is a problem that a malfunction such as malfunction of the integrated circuit occurs. In order to solve such a problem, it is necessary to design in consideration of a power supply voltage drop.

  As a power supply voltage drop analysis method, a method of analyzing by circuit simulation, a dynamic analysis method, and a static analysis method are known. The method of analysis by circuit simulation is the most accurate, but it is not possible to verify a large-scale semiconductor integrated circuit in particular due to constraints such as the computer simulation execution time and the storage capacity of the memory installed in the computer. is there. In addition, the dynamic analysis method has a problem that the scale of applicable semiconductor integrated circuits is limited and the modeling accuracy is low. From the above, a static analysis method is generally used (see Non-Patent Document 1).

In the static analysis method, the semiconductor integrated circuit is replaced with an equivalent circuit including a current source and a resistance element. First, the consumption current I _avg applied to the current source of the equivalent circuit is calculated (calculation of static average consumption current). Next, the resistance component R of the power supply wiring is extracted based on the mask layout data (extraction of the power supply wiring resistance network). Finally, a current source is added to the extracted resistance network and DC analysis is performed to obtain a voltage drop in the power supply wiring.

The power supply voltage drop ΔV _st by the static analysis method is
ΔV _st = I _avg × R (1)
It is.

  In static analysis methods, accurate analysis of large-scale semiconductor integrated circuits that could not be analyzed using circuit analysis and dynamic analysis methods is performed in real time. be able to. For this reason, the static analysis method has become the mainstream of the analysis method adopted in the current CAD tool for analyzing the power supply voltage drop.

  Now, in order to verify whether or not a semiconductor integrated circuit malfunctions due to a power supply voltage drop, it is generally considered to take into account changes in the delay time of signals input to and output from circuit elements (hereinafter referred to as delay changes). (See Patent Document 1).

The delay change occurs due to a power supply voltage drop, a voltage drop caused by ground wiring (hereinafter referred to as a ground voltage drop), and the like. If the value of the delay change associated with each circuit element exceeds the allowable delay change value that satisfies the design constraint conditions of the semiconductor integrated circuit, it is determined that the circuit element malfunctions.
JP 2000-195960 A Full-Chip Verification of UDSM Designs, Earl. Saleh (R. Saleh), Simplex Solutions, Signal Integrity Effects in Custom IC and ASIC Designs, Wiley Interscience, IEEE Press , 2002, pp.245-252.

  However, the delay calculation device disclosed in Patent Document 1 considers a delay change due to a power supply voltage drop, but does not consider a delay change due to a ground voltage drop. Was insufficient.

  In Patent Document 1, the delay time is calculated in consideration of the power supply voltage drop and the logic simulation of the semiconductor integrated circuit is performed, and the circuit element malfunctions based on the calculated delay time and the result of the logic simulation. It was determined whether or not. Therefore, when a malfunctioning circuit element is detected, it is necessary to repeat mask layout data correction, delay time calculation, and logic simulation until it is determined that the circuit element malfunctions. For this reason, there is a problem that the number of steps required for operation verification of the semiconductor integrated circuit increases.

  The present invention has been made in view of such circumstances. The allowable power supply voltage drop amount is used as a criterion for determining whether or not a circuit element included in a semiconductor integrated circuit malfunctions, and a power supply related to the type of circuit element. By calculating the allowable power supply voltage drop based on the relationship between the voltage drop, ground voltage drop, and delay variation, it is possible to verify the malfunction accurately and easily while considering the power supply voltage drop and ground voltage drop. An object of the present invention is to provide a circuit operation verification method and a computer program capable of performing the above.

  Another object of the present invention is to calculate the allowable power supply voltage drop based on the relationship between the power supply voltage drop, the ground voltage drop, and the delay variation stored in the storage means. It is another object of the present invention to provide a circuit operation verification method and a circuit operation verification apparatus capable of verifying a malfunction accurately, simply and at high speed while considering a ground voltage drop.

  Another object of the present invention is to more accurately calculate the allowable ground voltage drop amount based on the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount stored in the storage means. An object of the present invention is to provide a circuit operation verification device capable of verifying a malfunction.

  Another object of the present invention is to calculate a power supply voltage drop amount and a ground voltage drop amount related to a circuit element included in a semiconductor integrated circuit based on current consumption of the circuit element and resistances of the power supply wiring and the ground wiring. Accordingly, it is an object of the present invention to provide a circuit operation verification device that can consider a power supply voltage drop and a ground voltage drop without performing complicated calculations when verifying a malfunction.

  Still another object of the present invention is to calculate a delay change amount for calculating each of an allowable power supply voltage drop amount and an allowable ground voltage drop amount based on an input signal and an output signal to a circuit element. An object of the present invention is to provide a circuit operation verification device capable of considering a power supply voltage drop and a ground voltage drop without performing complicated calculations when verifying a malfunction.

  The circuit operation verification method according to the present invention is a circuit operation verification method for verifying whether or not a circuit element included in a semiconductor integrated circuit malfunctions by using a circuit operation verification apparatus. The power supply wiring and ground wiring included in the semiconductor integrated circuit A power supply connected to a circuit element included in the semiconductor integrated circuit by obtaining an allowable power supply voltage drop satisfying a design constraint condition of the semiconductor integrated circuit based on a power supply voltage drop amount and a ground voltage drop amount indicating a voltage drop due to each. When the power supply voltage drop amount indicating the voltage drop due to the wiring is determined whether or not the obtained allowable power supply voltage drop amount is exceeded, and it is determined that the power supply voltage drop amount is more than the allowable power supply voltage drop amount, It is determined that the circuit element malfunctions.

  In the circuit operation verification method according to the present invention, whether or not a circuit element included in a semiconductor integrated circuit malfunctions, a power supply voltage drop amount and a ground voltage indicating a voltage drop due to each of the power supply wiring and the ground wiring included in the semiconductor integrated circuit. A circuit operation verification method for verifying with a circuit operation verification apparatus having a storage means based on a drop amount, wherein the power supply voltage drop amount relating to a circuit element of the same type as the type of circuit element included in the semiconductor integrated circuit and the circuit element A relationship between a ground voltage drop amount and a delay change amount indicating a change due to the voltage drop in a delay time of a signal input / output to / from the circuit element of the type is stored in the storage unit and stored in the storage unit. The allowable power supply voltage drop amount is obtained based on the relationship and the given delay change amount, and the power supply voltage drop amount related to the circuit element included in the semiconductor integrated circuit is obtained. And judging the allowable whether the power is the voltage drop amount exceeds that is.

  In the circuit operation verification apparatus according to the present invention, whether or not a circuit element included in the semiconductor integrated circuit malfunctions is determined, a power supply voltage drop amount and a ground voltage indicating a voltage drop caused by the power supply wiring and the ground wiring included in the semiconductor integrated circuit, respectively. A circuit operation verification device for verifying based on a drop amount, the power supply voltage drop amount and the ground voltage drop amount relating to the same type of circuit element as the type of the circuit element included in the semiconductor integrated circuit, and the circuit of the type Storage means for storing a relationship of a delay change amount indicating a change due to the voltage drop of a delay time of a signal input / output to / from the element, the relationship stored in the storage means, and a given delay change amount Based on the allowable power supply voltage drop amount calculation means for obtaining the allowable power supply voltage drop amount, and the power supply voltage drop amount related to the circuit element included in the semiconductor integrated circuit is the allowable power supply voltage drop amount. Characterized in that it comprises a determination means for determining whether the amount calculating means is an allowable power supply voltage drop amount exceeds determined.

  The circuit operation verification apparatus according to the present invention includes an allowable ground voltage drop amount calculating means for obtaining an allowable ground voltage drop amount based on the relationship stored in the storage means and the given delay change amount; And an excess determining means for determining whether or not the ground voltage drop amount relating to the circuit element is an excess of the allowable ground voltage drop amount obtained by the allowable ground voltage drop amount calculating means.

  The circuit operation verification apparatus according to the present invention includes a power supply voltage drop amount calculating means for obtaining the power supply voltage drop amount related to the circuit element based on the current consumption of the circuit element and the resistance of the power supply wiring, and the current consumption And a ground voltage drop amount calculating means for determining the ground voltage drop amount related to the circuit element based on the resistance of the ground wiring, and the determining means is a power supply voltage obtained by the power supply voltage drop amount calculating means. It is determined whether or not a drop amount exceeds the allowable power supply voltage drop amount, and the excess determination means determines that the ground voltage drop amount obtained by the ground voltage drop amount calculation means is the allowable ground voltage. It is characterized in that it is determined whether or not the descent amount is exceeded.

  The circuit operation verification apparatus according to the present invention is based on an input signal and an output signal for the type of circuit element, and shows a delay indicating a change due to the voltage drop of a delay time of a signal input to and output from the type of circuit element. A delay change amount calculating means for obtaining a change amount, wherein the storage means stores the relationship between the power supply voltage drop amount and the ground voltage drop amount related to the circuit element of the type, and the delay change amount calculated by the delay change amount calculation means; It is characterized in that it is stored in the memory.

  The computer program according to the present invention is a computer program for determining whether or not a circuit element included in a semiconductor integrated circuit malfunctions in a computer and indicating a voltage drop caused by a power supply wiring and a ground wiring included in the semiconductor integrated circuit. A computer program for verifying based on a voltage drop amount, wherein the computer causes the power supply voltage drop amount and the ground voltage drop amount to be related to a circuit element of the same type as a circuit element included in the semiconductor integrated circuit, and An allowable power supply voltage drop amount is obtained based on a relationship between a delay change amount indicating a change due to the voltage drop of a delay time of a signal input / output to / from the type of circuit element and a given delay change amount. A power supply voltage drop amount relating to a circuit element included in the semiconductor integrated circuit is obtained in a step Characterized in that to execute the step of determining whether a pressure drop amount exceeded.

  In the present invention, the allowable power supply voltage drop that satisfies the design constraint conditions of the semiconductor integrated circuit is used as a criterion for determining whether or not a circuit element included in the semiconductor integrated circuit malfunctions. The allowable power supply voltage drop amount is, for example, the same type of power supply voltage drop amount and ground voltage drop amount related to the same type of circuit element as that of the semiconductor integrated circuit, and the same type of circuit element of the semiconductor integrated circuit. It is obtained on the basis of the relationship between the delay change amount indicating the change in the delay time of the signal input / output to / from the circuit element and the given delay change amount.

  Hereinafter, the power supply voltage drop amount and the ground voltage drop amount related to the same type of circuit element as the type of the circuit element included in the semiconductor integrated circuit are referred to as the power supply voltage drop amount and the ground voltage drop amount related to the type of the circuit element. A delay change amount indicating a change in delay time of a signal input / output to / from a circuit element of the same type as that of the circuit element included in the integrated circuit is referred to as a delay change amount according to the type of the circuit element.

The power supply voltage V _VDD applied to the circuit element in an ideal state where no voltage drop occurs is higher than the power supply voltage V _DD applied to the circuit element in a state where the voltage drop occurs, and the power supply voltage drop amount ΔV _DD is This is a difference between the power supply voltage V _VDD applied to the circuit element in an ideal state where no voltage drop occurs and the power supply voltage V _DD applied to the circuit element in a state where a voltage drop occurs.
V _VDD > V _DD (2)
ΔV _DD = V _VDD −V _DD (3)

In addition, the ground voltage V _VSS applied to the circuit element in an ideal state where no voltage drop occurs is lower than the ground voltage V _SS applied to the circuit element in a state where the voltage drop occurs, and the ground voltage drop amount ΔV _SS. Is the difference between the ground voltage V _SS applied to the circuit element in a state where a voltage drop occurs and the ground voltage V _VSS applied to the circuit element in an ideal state where no voltage drop occurs.
V _VSS <V _SS (4)
ΔV _SS = V _SS −V _VSS (5)

The change in the delay time is caused by a voltage drop caused by each of the power supply wiring and the ground wiring included in the semiconductor integrated circuit. Further, the delay time T _d in a state where a voltage drop occurs is longer than the delay time T _dd in an ideal state where no voltage drop occurs. The delay change amount P is, for example, the difference between the delay time T _d in a state where a voltage drop occurs and the delay time T _dd in an ideal state where no voltage drop occurs.
T _dd <T _d (6)
P = T _d −T _dd (7)

  The storage unit stores the relationship between the power supply voltage drop amount and the ground voltage drop amount related to the type of the circuit element, and the delay change amount related to the type of the circuit element. The relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of circuit element is a table of these values, a function obtained based on these values, and the like, for example, stored in the storage means in advance. Or calculated by a circuit operation verification device using a circuit simulator and stored in a storage means.

  The allowable power supply voltage drop amount calculating means calculates the allowable power supply voltage drop amount based on the relationship between the power supply voltage drop amount, the ground voltage drop amount and the delay change amount stored in the storage means, and the given delay change amount. Ask. As a given delay variation, a delay variation that satisfies the design constraint conditions of the semiconductor integrated circuit is generally used. For this reason, the obtained allowable power supply voltage drop amount is a power supply voltage drop amount that satisfies the design constraint conditions of the semiconductor integrated circuit.

  The determination unit determines whether or not the power supply voltage drop amount related to the circuit element included in the semiconductor integrated circuit exceeds the allowable power supply voltage drop amount. Here, the allowable power supply voltage drop amount is a determination criterion, and the power supply voltage drop amount related to the circuit element is a determination target. The power supply voltage drop amount related to the circuit element is stored in advance in a storage unit such as a memory or a hard disk included in the circuit operation verification device, or based on the mask layout data generated by the automatic placement and routing device, for example. Calculate with a verification device.

  When it is determined that the power supply voltage drop amount related to the circuit element exceeds the allowable power supply voltage drop amount, the delay change amount related to the circuit element exceeds the delay change amount satisfying the design constraint conditions of the semiconductor integrated circuit. It is determined that the element malfunctions.

  As described above, the circuit operation verification device verifies whether or not a circuit element included in the semiconductor integrated circuit malfunctions based on the power supply voltage drop amount and the ground voltage drop amount.

  In the present invention, the allowable ground voltage drop that satisfies the design constraint conditions of the semiconductor integrated circuit is used as a criterion for determining whether or not a circuit element included in the semiconductor integrated circuit malfunctions. The allowable ground voltage drop amount is obtained based on, for example, the relationship between the power supply voltage drop amount and ground voltage drop amount related to the type of circuit element, the delay change amount related to the type of circuit element, and the given delay change amount. It is done.

  The allowable ground voltage drop amount calculation means calculates the allowable ground voltage drop amount based on the relationship between the power supply voltage drop amount, the ground voltage drop amount and the delay change amount stored in the storage means, and the given delay change amount. Ask. Therefore, the obtained allowable ground voltage drop amount is the ground voltage drop amount that satisfies the design constraint conditions of the semiconductor integrated circuit.

  The excess determination means determines whether or not the ground voltage drop amount related to the circuit element included in the semiconductor integrated circuit exceeds the allowable ground voltage drop amount. Here, the allowable ground voltage drop amount is a determination criterion, and the ground voltage drop amount related to the circuit element is a determination target. For example, the ground voltage drop amount related to the circuit element is stored in advance in a storage unit included in the circuit operation verification apparatus, or is calculated by the circuit operation verification apparatus based on the mask layout data generated by the automatic placement and routing apparatus. .

  When it is determined that the ground voltage drop amount related to the circuit element exceeds the allowable ground voltage drop amount, the delay change amount related to the circuit element exceeds the delay change amount satisfying the design constraint condition of the semiconductor integrated circuit. It is determined that the element malfunctions.

  The determination means determines that the power supply voltage drop amount related to the circuit element is less than or equal to the allowable power supply voltage drop amount. Further, the excess determination means determines that the ground voltage drop amount related to the circuit element is less than or equal to the allowable ground voltage drop amount. Is determined, the circuit element is determined not to malfunction.

  As described above, the circuit operation verification device verifies whether or not a circuit element included in the semiconductor integrated circuit malfunctions based on the power supply voltage drop amount and the ground voltage drop amount.

  In the present invention, the power supply voltage drop amount used for the judgment by the judging means is obtained based on the current consumption of the circuit element and the resistance of the power supply wiring, and the ground used for the judgment by the excess judging means. The voltage drop amount is calculated by the ground voltage drop amount calculation means based on the current consumption of the circuit element and the resistance of the ground wiring. Each of such power supply voltage drop amount and ground voltage drop amount is calculated by using, for example, a known wiring parasitic element extraction tool, power consumption analysis tool, DC analysis tool, or the like.

  In the present invention, the delay change amount calculating means obtains the delay change amount in order to store the relationship among the power supply voltage drop amount, the ground voltage drop amount and the delay change amount according to the type of circuit element in the storage means. The delay variation calculation means is based on a voltage drop of a delay time of a signal input / output to / from this circuit element based on an input signal and an output signal to the same type of circuit element as the type of the circuit element included in the semiconductor integrated circuit. A delay change amount indicating a change is obtained.

  For example, the input signal is given in advance, and the output signal is calculated by using a known circuit simulator. The power supply voltage drop amount and the ground voltage drop amount stored in the storage means are, for example, the sum of the power supply voltage drop amount and the ground voltage drop amount under the condition that the power supply voltage drop amount and the ground voltage drop amount are equal. Is given in advance, or a plurality is appropriately generated.

  According to the circuit operation verification method and the circuit operation verification apparatus of the present invention, the allowable power supply voltage drop amount satisfying the design constraint conditions of the semiconductor integrated circuit is obtained based on the power supply voltage drop amount and the ground voltage drop amount, and the obtained allowable voltage is obtained. The amount of power supply voltage drop is used as a criterion for determining whether or not a circuit element malfunctions. For this reason, it is possible to accurately verify the malfunction while considering the power supply voltage drop and the ground voltage drop.

  The allowable power supply voltage drop amount is based on, for example, the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of circuit element, and the delay change amount that satisfies the design constraint conditions of the semiconductor integrated circuit. Desired. The amount of delay change that satisfies the design constraint conditions of the semiconductor integrated circuit is given, and the relationship among the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of circuit element is obtained using, for example, a known CAD tool. This eliminates the need for complicated calculations.

  Further, the relationship between the power supply voltage drop amount, the ground voltage drop amount and the delay change amount related to the type of circuit element is stored in the storage means, and the allowable power supply voltage drop amount is obtained based on the relationship stored in the storage means. Therefore, it is possible to verify the malfunction simply and at high speed while considering the power supply voltage drop and the ground voltage drop.

  Furthermore, when determining whether or not a circuit element malfunctions, for example, a logic simulation is unnecessary, so that malfunction can be verified simply and at high speed.

  Further, when it is determined that the circuit element malfunctions, when the mask layout data is corrected and the circuit operation verification is performed again, the power supply voltage drop amount related to the determination target, that is, the circuit element is determined according to the correction of the mask layout data. The relationship among the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount stored in the storage means can be reused without being changed in accordance with the correction of the mask layout data. That is, the allowable power supply voltage drop amount that is the criterion is not required to be recalculated or can be recalculated easily and at high speed. For this reason, the process required for the operation verification of the semiconductor integrated circuit can be reduced.

  According to the circuit operation verification device of the present invention, for example, the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of circuit element, and a given delay change that satisfies the design constraint conditions of the semiconductor integrated circuit. The allowable ground voltage drop amount that satisfies the design constraint condition of the semiconductor integrated circuit is obtained based on the amount, and the obtained allowable ground voltage drop amount is used as a criterion for determining whether or not the circuit element malfunctions. For this reason, it is possible to verify the malfunction more accurately while considering the power supply voltage drop and the ground voltage drop.

  Further, the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount related to the type of circuit element is stored in the storage means, and the allowable ground voltage drop amount is obtained based on the relationship stored in the storage means. Therefore, it is possible to verify the malfunction simply and at high speed while considering the power supply voltage drop and the ground voltage drop.

  Further, when determining whether or not a circuit element malfunctions, for example, logic simulation is unnecessary, and therefore malfunction can be verified easily and at high speed.

  Furthermore, when it is determined that the circuit element malfunctions, when the mask layout data is corrected and the circuit operation verification is performed again, according to the correction of the mask layout data, the determination target, that is, the ground voltage drop amount related to the circuit element The relationship among the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount stored in the storage means can be reused without being changed in accordance with the correction of the mask layout data. . That is, it is not necessary to recalculate the allowable ground voltage drop amount that is a criterion, or it can be recalculated simply and at high speed. For this reason, the process required for the operation verification of the semiconductor integrated circuit can be reduced.

  According to the circuit operation verification apparatus of the present invention, the power supply voltage drop amount and the ground voltage drop amount to be compared with the allowable power supply voltage drop amount and the allowable ground voltage drop amount are respectively determined using, for example, a known CAD tool. Therefore, the power supply voltage drop and the ground voltage drop can be taken into consideration without performing complicated calculations.

  According to the circuit operation verification apparatus of the present invention, in order to store the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount in the storage means, the delay change amount is obtained using, for example, a known CAD tool. be able to. As a result, the power supply voltage drop and the ground voltage drop can be taken into consideration without performing complicated calculations.

  Further, when it is determined that the circuit element malfunctions, it is not necessary to calculate the delay variation again when correcting the mask layout data and performing the circuit operation verification again. For this reason, the process required for the operation verification of the semiconductor integrated circuit can be reduced.

  According to the computer program of the present invention, the allowable power supply voltage drop amount calculating means, the determining means, etc. of the circuit operation verification device are realized by software using computer hardware elements, and the computer is converted into the data output device of the present invention. Can function as.

  Further, the computer program can be stored and distributed in a portable recording medium, or can be distributed via a communication line, or can be stored in advance in a storage unit (for example, ROM) included in the computer. I can keep it. Such a computer program may be executed after being installed in a volatile or nonvolatile storage unit (such as a RAM or a hard disk), or may be read from a recording medium or a distribution source and executed directly.

  Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.

  FIG. 1 is a block diagram showing a configuration of a circuit operation verification apparatus 1 according to the present invention. The circuit operation verification apparatus 1 uses a computer such as a personal computer, for example, and includes a CPU 10, a ROM 11, and a RAM 12 that are control centers of the circuit operation verification apparatus 1. The circuit operation verification apparatus 1 includes a display unit 13 using a CRT display, a liquid crystal display, etc., an operation unit 14 using a keyboard, a mouse, etc., an external storage unit 15 using a CD-ROM drive, and a hard disk An auxiliary storage unit 16 is provided.

  In the figure, reference numeral 2 denotes a portable recording medium such as a CD-ROM, in which the computer program and data of the present invention are recorded. When installing the computer program and data recorded in the recording medium 2 into the computer, the external storage unit 15 included in the computer is controlled by the CPU 10 to read out the computer program and data from the recording medium 2. The read computer program and data are stored in the auxiliary storage unit 16. By installing the computer program and data stored in the recording medium 2, the computer functions as the circuit operation verification device 1.

  The CPU 10 provided in the computer is connected to each part of the apparatus via a bus, a signal line, etc., and uses the RAM 12 as a work area according to the computer program and data stored in advance in the ROM 11 or stored in the auxiliary storage unit 16. Then, each part of the apparatus is controlled and various processes are executed.

  The condition storage unit 161, the relationship storage unit 162, the determination target storage unit 163, the determination reference storage unit 164, and the determination result storage unit 165 are different parts of the storage area of the auxiliary storage unit 16, respectively. In the condition storage unit 161, for example, data read from the recording medium 2 or a recording medium other than the recording medium 2 by the external storage unit 15, data input via the operation unit 14, and reception via a communication line (not shown) The data given from the outside of the circuit operation verification device 1 such as the data thus obtained is stored. In the present embodiment, the relationship storage unit 162 to the determination result storage unit 165 store data calculated by the circuit operation verification device 1.

  FIG. 2 is a layout diagram showing the configuration of the semiconductor integrated circuit 3 to be verified using the circuit operation verification apparatus 1. The semiconductor integrated circuit 3 forms a plurality of circuit elements 31, 31,..., Power wirings 32, 32,..., Ground wirings 33, 33,. Do it. The semiconductor integrated circuit 3 includes a predetermined number of circuit elements 31, 31,..., Such as inverter elements and diode elements. The circuit element 31 is connected to a power supply wiring 32 and a ground wiring 33, and the power supply wirings 32, 32,... And the ground wirings 33, 33,.

When the operation verification of the semiconductor integrated circuit 3 is performed, the circuit operation verification device 1 verifies whether or not each circuit element 31, 31,... At this time, the CPU 10 of the circuit operation verification apparatus 1 executes an operation verification process shown in FIG. In the operation verification process, for each circuit element 31, 31,..., _{Whether the} power supply voltage drop amount ΔV _DDDC related to the circuit element 31 exceeds the allowable power supply voltage drop amount ΔV _DDY that satisfies the design constraint conditions of the semiconductor integrated circuit 3 It is determined whether or not. Further, for each circuit element 31, 31,..., It is determined whether or not the ground voltage drop amount ΔV _SSDC related to the circuit element 31 exceeds the allowable ground voltage drop amount ΔV _SSY that satisfies the design constraint conditions of the semiconductor integrated circuit 3. Is done.

Here, the power supply voltage drop amount ΔV _DDDC and the ground voltage drop amount ΔV _SSDC related to the circuit element 31 are obtained by a determination target calculation process shown in FIG. 9 to be described later using a known static analysis method. The mask layout data of the semiconductor integrated circuit 3 required in this case is generated in advance by, for example, an automatic placement and routing apparatus (not shown), stored in a recording medium, read from the recording medium, and stored in the auxiliary storage unit 16. Is done. In addition to the mask layout data, simulation conditions such as a delay change amount P _Y and a measurement voltage Vc, which will be described later, are also stored in the condition storage unit 161 by being read from the recording medium or input via the operation unit 14, for example. The That is, the mask layout data and simulation conditions are given from the outside of the circuit operation verification apparatus 1. The allowable power supply voltage drop amount ΔV _DDY and the allowable ground voltage drop amount ΔV _SSY are obtained by the circuit operation verification device 1 (described later).

When the power supply voltage drop amount ΔV _DDDC exceeds the allowable power supply voltage drop amount ΔV _DDY or when the ground voltage drop amount ΔV _SSDC exceeds the allowable ground voltage drop amount ΔV _SSY , the circuit element 31, and consequently the semiconductor integrated circuit 3, Determined to malfunction. On the other hand, if the power supply voltage drop amount ΔV _DDDC is less than or equal to the allowable power supply voltage drop amount ΔV _DDY and the ground voltage drop amount ΔV _SSDC is less than or equal to the allowable ground voltage drop amount ΔV _SSY, it is determined that the circuit element 31 will not malfunction. When it is determined that all the circuit elements 31, 31,... Do not malfunction, it is determined that the semiconductor integrated circuit 3 does not malfunction.

  The determination result of whether each circuit element 31 malfunctions is stored in the determination result storage unit 165 in association with each circuit element 31.

  The circuit shown in FIG. 3 is an equivalent circuit 300 for voltage drop analysis of the semiconductor integrated circuit 3. In the equivalent circuit 300 related to the power supply wirings 32, 32,..., The circuit elements 31, 31,... Of the semiconductor integrated circuit 3 are replaced with current sources 310, 310,. Are replaced with resistance elements 321, 321,... Corresponding to the wiring resistances 32,. Further, although not shown, the equivalent circuit related to the ground wirings 33, 33,... Replaces the circuit elements 31, 31,... Of the semiconductor integrated circuit 3 with current sources, and replaces the ground wirings 33, 33,. , 33,... Are replaced with a resistance element corresponding to the wiring resistance and a capacitance element corresponding to the wiring capacitance.

The CPU 10 extracts a resistance component R _D of the power supply wirings 32, 32,... With respect to the equivalent circuit 300 related to the power supply wirings 32, 32,. Extraction of power wiring resistance network). Similarly, the CPU 10 extracts a resistance component R _S of the ground wirings 33, 33,... Based on the mask layout data using the wiring parasitic element extraction tool for the equivalent circuit related to the ground wirings 33, 33,. Extraction of wiring resistance network).

Further, the CPU 10 calculates a consumption current I _Davg applied to each current source 310 of the equivalent circuit 300 related to the power supply wirings 32, 32,..., And similarly each current source of the equivalent circuit related to the ground wirings 33, 33 _,. Current consumption I _{Savg applied} to the current is calculated (calculation of static average current consumption). Current consumption I _Davg, I _savg is a known power analysis tool is calculated based on an average number of signal changes N. The average signal change count N is obtained based on the activation rate or the signal transition probability with respect to the clock signal transition, and is stored in advance in the condition storage unit 161 as a simulation condition.

Further, the CPU 10 obtains the power supply voltage drop and the ground voltage drop by performing DC analysis by adding a current source to each of the extracted power supply wiring resistance network and wiring wiring resistance network. Specifically, the CPU 10 uses the DC analysis tool to relate each circuit element 31 based on the resistance component R _D of the power supply wirings 32, 32,... And the current consumption I _Davg of the current sources 310, _310,. Calculate the power supply voltage drop ΔV _DDDC . here,
ΔV _DDDC = I _Davg × R _D (8)
This relationship holds.

Further, the CPU 10 calculates a ground voltage drop amount ΔV _SSDC related to each circuit element 31 based on the resistance component R _S of the ground wirings 33, 33,... And the consumption current I _Savg using a DC analysis tool. here,
ΔV _SSDC = I _Savg × R _S (9)
This relationship holds.

The calculated power supply voltage drop amount ΔV _DDDC and ground voltage drop amount ΔV _SSDC are stored in the determination target storage unit 163 in association with each circuit element 31.

  The wiring parasitic element extraction tool, power consumption analysis tool, and DC analysis tool software used above are read from the recording medium 2 and stored in the auxiliary storage unit 16, for example.

The allowable power supply voltage drop amount ΔV _DDY and the allowable ground voltage drop amount ΔV _SSY that satisfy the design constraint conditions of the semiconductor integrated circuit 3 are the delay change amount P _Y (the constraint value of the delay change amount) that satisfies the design constraint conditions of the semiconductor integrated circuit 3. And the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of the circuit element 31 are calculated in the operation verification process. The relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of the circuit element 31 is obtained by a determination criterion calculation process shown in FIGS. 7 and 8 to be described later. The function ΔV (P) shown in FIG. The delay change amount P _Y is stored in advance in the condition storage unit 161 as a simulation condition.

The allowable power supply voltage drop ΔV _DDY and the allowable ground voltage drop ΔV _SSY are
ΔV _DDY = ΔV _SSY = ΔV (P _Y ) / 2 (10)
And The calculated allowable power supply voltage drop amount ΔV _DDY and allowable ground voltage drop amount ΔV _SSY are stored in the determination criterion storage unit 164.

  FIG. 4 is a circuit diagram showing a configuration of the circuit element 31 of the semiconductor integrated circuit 3, and FIG. 5 is an explanatory diagram showing a delay change related to the circuit element 31. Hereinafter, as the circuit element 31, an inverter element is illustrated. The circuit element 31, which is an inverter element, includes a terminal IN that receives an input signal and a terminal OUT that outputs an output signal, and is connected to a power supply wiring 32 and a ground wiring 33.

In an ideal state where a power supply voltage drop due to the power supply wiring 32 and a ground voltage drop due to the ground wiring 33 do not occur, the power supply voltage _VVDD is applied to the power supply wiring 32 side of the circuit element 31 and the ground voltage V is applied to the ground wiring 33 side. _VSS is applied. However, since a power supply voltage drop and a ground voltage drop actually occur, the power supply voltage V _DD is applied to the circuit element 31 on the power supply wiring 32 side, and the ground voltage V _SS is applied to the ground wiring 33 side. In this case, power supply voltage drop amount (power supply voltage swing) ΔV _DD and ground voltage drop amount (ground voltage swing) ΔV _SS are
ΔV _DD = V _VDD −V _DD > 0 (11)
ΔV _SS = V _SS −V _VSS > 0 (12)
It is.

That relates to a power supply line 32 side, the voltage of the power supply is connected to the power supply line 32 is the V _VDD, the power supply voltage V _VDD to the power supply line 32 side of the circuit element 31 the voltage drop [Delta] V _DD occurs from V _VDD is Applied. A similarly ground line 33 side, the voltage of the ground is connected to the ground line 33 is the V _VSS, V _VSS with respect to the ground to the ground wiring 33 side of the circuit element 31 occurs a voltage drop of - [Delta] V _SS The voltage V _SS is applied.

In the present embodiment,
ΔV _DD = ΔV _SS > 0 (13)
Hereinafter, the sum ΔV of the power supply voltage drop amount ΔV _DD and the ground voltage drop amount ΔV _SS is referred to as the total voltage drop amount.
ΔV = ΔV _DD + ΔV _SS (14)

  The horizontal axis in FIG. 5 is time T [ps], and the vertical axis is voltage V [V]. The input signal 51 in an ideal state in which the power supply voltage drop by the power supply wiring 32 and the ground voltage drop by the ground wiring 33 do not occur. The waveforms of the output signal 52 and the waveforms of the input signal 53 and the output signal 54 in a state where a power supply voltage drop and a ground voltage drop occur are shown.

In this embodiment, the measurement voltage Vc for measuring the delay time is
Vc = V _VDD / 2 (15)
And In this case, the delay time T12 of the output signal 52 with respect to the input signal 51 and the delay time T34 of the output signal 54 with respect to the input signal 53 are as shown in FIG.
T12 = T2-T1 (16)
T34 = T3-T1 (17)
It is.

The measurement voltage Vc, the power supply voltage V _VDD , and the ground voltage V _VSS are stored in advance in the condition storage unit 161 as simulation conditions. Further, as the total voltage drop amount ΔV, there are K different total voltage drop amounts ΔV _k (K is a natural number where _k ≦ K. ΔV _{k −1} <ΔV _k ) (K is a constant of a natural number, hereinafter K = 5). Pre-given. Specifically, a difference D between the total voltage drop amount ΔV _k and the total voltage drop amount ΔV _k−1 is stored in the condition storage unit 161 in advance as a simulation condition.
ΔV _k = ΔV ₀ + k × D (18)
Is required. However, ΔV ₀ is a total voltage drop amount in an ideal state in which a power supply voltage drop and a ground voltage drop do not occur.
ΔV ₀ = 0 (19)
It is.

The total voltage drop amount ΔV _k is the sum of the power supply voltage drop amount ΔV _DDk and the ground voltage drop amount ΔV _SSk .
ΔV _k = ΔV _DDk + ΔV _SSk (20)

Further, based on the formulas (11) to (13), the following formulas (21) to (23) regarding the power supply voltage V _DDk and the ground voltage V _SSk , and the power supply voltage drop amount ΔV _DDk and the ground voltage drop amount ΔV _SSk. Is established.
ΔV _DDk = V _VDD −V _DDk > 0 (21)
ΔV _SSk = V _SSk −V _VSS > 0 (22)
ΔV _DDk = ΔV _SSk > 0 (23)

In the present embodiment, for the sake of simplification of explanation, the value of the difference D between ΔV _k and ΔV _k−1 is constant, but the present invention is not limited to this.

From Equations (18) to (23), the power supply voltage V _DDk and the ground voltage V _SSk are
V _DDk = V _VDD −ΔV _DDk = V _VDD −ΔV _k / 2 (24)
V _SSk = V _VSS + ΔV _SSk = V _VSS + ΔV _k / 2 (25)
It is.

From the above, in the input signal 51 and the output signal 52 in an ideal state where no voltage drop occurs, the maximum voltage V _la is the power supply voltage V _VDD and the minimum voltage V _sm is the ground voltage V _VSS . Further, in the input signal and the output signal (for example, the input signal 53 and the output signal 54) in a state where the voltage drop has occurred, the maximum voltage is the power supply voltage V _DDk and the minimum voltage is the ground voltage V _SSk .

Further, the delay time of the output waveform with respect to the input waveform in a state where the voltage drop has occurred is assumed to be T _dk (T _dk−1 <T _dk ). The delay time T _dk of the output waveform 54 with respect to the input waveform 53 is T 34. The delay time of the output waveform 52 with respect to the input waveform 51 in an ideal state where no voltage drop occurs is T _d0 (T _d0 = T12).

An output signal from the circuit element 31 with respect to an input signal of the maximum voltage V _la and the minimum voltage V _sm input to the circuit element 31 is obtained using a circuit simulator. However, the input signal dullness of the input signal is selected so that the sensitivity to the delay change is the most severe. By doing so, when the verification in the semiconductor integrated circuit 3 is performed, the slope of the change of the delay time with respect to the power supply voltage drop and the ground voltage drop, that is, the sensitivity becomes the most severe, and the worst condition for the delay change amount is set. Covered leak-free detection can be performed. The circuit simulator software is read from, for example, the recording medium 2 and stored in the auxiliary storage unit 16.

In the present embodiment, the delay variation P _k when the total voltage drop ΔV changes from the total voltage drop ΔV ₀ to the total voltage drop ΔV _k is expressed as follows:
P _k = (T _dk −T _d0 ) / T _d0 × 100 (26)
And Further, the delay change amount P ₀ in an ideal state where the power supply voltage drop and the ground voltage drop do not occur is
P ₀ = 0 (27)
It is.

When the total voltage drop amount ΔV _k increases, that is, when the power supply voltage drop amount ΔV _DDk and the ground voltage drop amount ΔV _SSk increase, the delay time T _dk and thus the delay change amount P _k increases.

Table 1 shows the total voltage drop amount ΔV _k [V] including the relationship between the total voltage drop amount ΔV ₀ [V], the delay time T _d0 [ps], and the delay change amount P ₀ [%], and the delay time T _dk. The relationship between [ps] and delay variation P _k [%] is shown. In the relation storage unit 162, the total voltage drop amounts ΔV ₀ and ΔV _k , the delay times T _d0 and T _dk , and the delay change amounts P ₀ and P _k are stored in association with each other as shown in Table 1. That is, the relationship storage unit 162 functions as a storage unit that stores the relationship between the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of the circuit element 31.

FIG. 6 is a characteristic diagram showing the relationship between the delay variation amount and the total voltage drop amount related to the circuit element 31. The horizontal axis of FIG. 6 is the delay change amount P [%], and the vertical axis is the total voltage drop amount ΔV [V]. As shown in FIG. 6, since the relationship between the delay change amount P and the total voltage drop amount ΔV is substantially linear, the point (P _k−1 , ΔV _k−1 ) and the point (P _k , ΔV _k ) A function ΔV (P) obtained by linearly interpolating the gap is obtained.

Table 2 shows the correspondence between the delay variation range P _k ≦ P ≦ P _k-1 (indicated as P _{k-1 to} P _{k in} Table 2) and the function ΔV (P). Within the range of P _k ≦ P ≦ P _k−1 ,
ΔV (P) = (ΔV _k −ΔV _k−1 ) / (P _k −P _k−1 ) × P
_{+ (ΔV k-1 × P} k -ΔV k × P k-1) / (P k -P k-1) (28)
It is.

Below,
A = (ΔV _k −ΔV _k−1 ) / (P _k −P _k−1 ) (29)
B = (ΔV _k−1 × P _k −ΔV _k × P _k−1 ) / (P _k −P _k−1 ) (30)
And A is a coefficient of P in the function ΔV (P), and B is a constant. That is, Equation (28) is
ΔV (P) = A × P + B (31)
It is.

Table 2 shows the correspondence between the range P ≧ P _K (indicated by P _{5 in} Table 2) and the function ΔV (P). Within the range of P ≧ P _K
ΔV (P) = (ΔV _K −ΔV _K−1 ) / (P _K −P _K−1 ) × P
+ (ΔV _K-1 × P _K −ΔV _K × P _K-1 ) / (P _K −P _K-1 ) (32)
It is.

The relationship storage unit 162 stores the delay variation range P _k ≦ P ≦ P _k−1 and the function ΔV (P) in association with each other as shown in Table 2. That is, the relationship storage unit 162 functions as a storage unit that stores a function ΔV (P) that is a relationship among the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount according to the type of the circuit element 31. When the value of the delay change amount P is determined, the value of the total voltage drop amount ΔV is calculated by using the function ΔV (P). That is, the total maximum voltage drop amount ΔV _Y = ΔV (P _Y ) obtained by substituting P = P _Y into the function ΔV (P) based on the delay change amount P _Y that satisfies the design constraint conditions of the semiconductor integrated circuit 3. Further, the allowable power supply voltage drop amount ΔV _DDY and the allowable ground voltage drop amount ΔV _SSY are calculated based on Expression (10).

When the power supply voltage drop amount ΔV _DDDC exceeds the allowable power supply voltage drop amount ΔV _DDY or when the ground voltage drop amount ΔV _SSDC exceeds the allowable ground voltage drop amount ΔV _SSY , the delay change amount P of the semiconductor integrated circuit 3 Exceeds the delay variation P _Y that satisfies the design constraint conditions of the semiconductor integrated circuit 3. For this reason, it is determined that the circuit element 31 and thus the semiconductor integrated circuit 3 malfunctions. On the other hand, when the power supply voltage drop amount ΔV _DDDC is less than or equal to the allowable power supply voltage drop amount ΔV _DDY and the ground voltage drop amount ΔV _SSDC is less than or equal to the allowable ground voltage drop amount ΔV _SSY , the delay change amount P of the semiconductor integrated circuit 3 Is less than or equal to the delay variation P _{Y that} satisfies the design constraint conditions of the semiconductor integrated circuit 3. For this reason, it is determined that the circuit element 31 does not malfunction.

  Hereinafter, a determination criterion calculation process, a determination target calculation process, and an operation verification process executed by the CPU 10 with respect to one circuit element 31 will be described. As for the other circuit elements 31, 31,..., Each process may be executed in the same manner as the determination criterion calculation process, the determination target calculation process, and the operation verification process related to one circuit element 31. Therefore, data stored in the relationship storage unit 162 to the determination result storage unit 165 in the determination criterion calculation process, the determination target calculation process, and the operation verification process are stored in association with the corresponding circuit elements 31.

  FIG. 7 and FIG. 8 are flowcharts showing the procedure of the determination criterion calculation process executed by the CPU 10 of the circuit operation verification apparatus 1. The determination criterion calculation process is executed, for example, when an operator of the circuit operation verification apparatus 1 inputs a circuit operation verification command to the circuit operation verification apparatus 1 via the operation unit 14 of the circuit operation verification apparatus 1.

The CPU 10 substitutes “0” for the total voltage drop amount ΔV ₀ (S11), reads the power supply voltage V _VDD and the ground voltage V _VSS from the condition storage unit 161, and sets the maximum voltage V _la = V _VDD and the minimum voltage V _sm. = V _VSS input signal 51 is generated (S12), and an output signal 52 is calculated using a circuit simulator (S13).

Further, the CPU 10 reads the measured voltage Vc from the condition storage unit 161, and calculates the delay time _Td0 based on the input signal 51 generated in S12, the output signal 52 calculated in S13, and the measured voltage Vc (S14). . Further, the CPU 10 substitutes “0” for the delay variation P ₀ (S15). Furthermore, the CPU 10 stores the total voltage drop amount ΔV ₀ , the delay time T _d0 , and the delay change amount P ₀ in the relationship storage unit 162 in association with the circuit element 31 (S16).

  The CPU 10 substitutes “1” for the variable k (S17).

The CPU 10 reads the difference D from the condition storage unit 161, and calculates the total voltage drop amount ΔV _k based on the read difference D, the total voltage drop amount ΔV _{0 of} S11, and the equation (18) (S18). Then CPU10 is total amount of voltage drop [Delta] V _k and formulas (24) calculated in the condition storage unit 161 the power supply voltage V _VDD and the ground voltage V _VSS and S18 read from and based on the equation (25), the supply voltage V _DDk and ground voltage V _VSS are calculated, an input signal with maximum voltage V _la = V _DDk and minimum voltage V _sm = V _VSS is generated (S19), and an output signal is calculated using a circuit simulator (S20).

Further, the CPU 10 calculates the delay time T _dk based on the measured voltage Vc read from the condition storage unit 161, the input signal generated in S19, and the output signal calculated in S20 (S21). Further, the CPU 10 calculates the delay change amount P _k based on the delay time T _dk calculated in S21, the delay time T _d0 calculated in S14, and Equation (26) (S22). Furthermore, the CPU 10 stores the total voltage drop amount ΔV _k , the delay time T _dk , and the delay change amount P _k in the relationship storage unit 162 in association with the circuit element 31 (S23).

Further, the CPU 10 reads the total voltage drop amounts ΔV _k , ΔV _k−1 and the delay variation amounts P _k , P _k−1 from the relationship storage unit 162, generates a function ΔV (P) based on the equation (28), The range P _k ≦ P ≦ P _k−1 and the function ΔV (P) are associated with the circuit element 31 and stored in the relationship storage unit 162 (S24). More specifically, in S24, the range P _k ≦ P ≦ P _k−1 , the coefficient A, and the constant B are stored in the relationship storage unit 162 based on the mathematical expressions (29) and (30).

  The CPU 10 determines whether or not the variable k is equal to or greater than the constant K (S25). If k <K (NO in S25), the CPU increments the variable k (S26) and returns the process to S18.

When the variable k is equal to or greater than the constant K (YES in S25), the CPU 10 generates the function ΔV (P) based on the equation (32), and sets the range P ≧ P _K and the function ΔV (P) to the circuit element 31. In the relation storage unit 162 (S27), and the determination criterion calculation process is terminated.

  FIG. 9 is a flowchart illustrating a determination target calculation process performed by the CPU 10 of the circuit operation verification apparatus 1. The determination target calculation process is executed after the determination criterion calculation process ends.

The CPU 10 reads the mask layout data from the auxiliary storage unit 16 (S31), extracts the resistance component _RD using the wiring parasitic element extraction tool based on the read mask layout data (S32), and further the condition storage unit 161. The number N of signal changes is read out from (S33), and the current consumption I _Davg is calculated using the power consumption analysis tool based on the read number N of signal changes (S34). Next, the CPU 10 calculates the power supply voltage drop amount ΔV _DDDC using the DC analysis tool based on the resistance component R _D and the consumption current I _Davg and stores it in the determination target storage unit 163 in association with the circuit element 31 (S35). .

Furthermore, the CPU 10 extracts the resistance component R _S using the wiring parasitic element extraction tool based on the mask layout data read from the condition storage unit 161 in S31 (S36), and further, the condition storage unit 161 in S33. Based on the signal change count N read out from, the current consumption I _Savg is calculated using the power consumption analysis tool (S37). Next, the CPU 10 calculates a ground voltage drop amount ΔV _SSDC using a DC analysis tool based on the resistance component R _S and the consumption current I _Savg and stores it in the determination target storage unit 163 in association with the circuit element 31 (S38). .

  After completion of S38, the CPU 10 ends the determination target calculation process.

  FIG. 10 is a flowchart showing the procedure of the operation verification process executed by the CPU 10 of the circuit operation verification apparatus 1. The operation verification process is executed after the determination target calculation process ends.

The CPU 10 reads the delay change amount P _Y from the condition storage unit 161 (S51), substitutes the read delay change amount P _Y into the function ΔV (P) stored in the relationship storage unit 162, and determines the total maximum voltage drop. The amount ΔV _Y is obtained (S52). More specifically, the CPU 10 reads the coefficient A and the constant B stored in the relationship storage unit 162 in association with the delay variation P _Y read in S51, and formulas P _k−1 ≦ P _Y ≦ P _k. ΔV _Y is obtained based on (31). However, when P = P _Y ≧ P _K , the CPU 10 obtains the total maximum voltage drop amount ΔV _Y based on P = P _Y and Expression (32).

Further, the CPU 10 obtains the allowable power supply voltage drop amount ΔV _DDY based on the total maximum voltage drop amount ΔV _Y = ΔV (P _Y ) obtained in S52 and the equation (10), and stores the determination reference in association with the circuit element 31. 164 (S53). Similarly, based on the total maximum voltage drop amount ΔV _Y = ΔV (P _Y ) obtained in S52 and the equation (10), the allowable ground voltage drop amount ΔV _SSY is obtained, The determination reference storage unit 164 stores the information in association with the element 31 (S54).

The CPU 10 reads the power supply voltage drop amount ΔV _DDDC from the determination target storage unit 163, further reads the allowable power supply voltage drop amount ΔV _DDY from the determination reference storage unit 164 (S55), and the read power supply voltage drop amount ΔV _DDDC is the allowable power supply voltage. It is determined whether or not the drop amount ΔV _DDY is exceeded (S56). When power supply voltage drop amount ΔV _DDDC > allowable power supply voltage drop amount ΔV _DDY (YES in S56), the CPU 10 determines that the circuit element 31 malfunctions (S57), and associates the determination result that malfunction occurs with the circuit element 31. And stored in the determination result storage unit 165 (S58).

When power supply voltage drop amount ΔV _DDDC ≦ allowable power supply voltage drop amount ΔV _DDY (NO in S56), CPU 10 reads ground voltage drop amount ΔV _SSDC from determination target storage unit 163, and further permits allowable grounding from determination reference storage unit 164. The voltage drop amount ΔV _SSY is read (S59), and it is determined whether or not the read ground voltage drop amount ΔV _SSDC exceeds the allowable ground voltage drop amount ΔV _SSY (S60). When ground voltage drop ΔV _SSDC > allowable ground voltage drop ΔV _SSY (YES in S60), CPU 10 determines in S57 that the circuit element 31 malfunctions, and in S58, the determination result that malfunction occurs. Is stored in the determination result storage unit 165 in association with the circuit element 31.

When the ground voltage drop amount ΔV _SSDC ≦ allowable ground voltage drop amount ΔV _SSY (NO in S60), the CPU 10 determines that the circuit element 31 is a normal circuit element that does not malfunction (S61), and in S58. The determination result that is normal is associated with the circuit element 31 and stored in the determination result storage unit 165.

  After completing the process of S58, the CPU 10 ends the operation verification process. Note that the determination result stored in the determination result storage unit 165 in S58 may be displayed on the display unit 13 before the operation verification process ends.

When the design constraint condition of the semiconductor integrated circuit 3 is changed, the value of the delay variation P _Y is changed according to the changed design constraint condition. The CPU 10 executes an operation verification process based on the changed delay change amount P _Y. In this case, it is not necessary to execute the determination criterion calculation process and the determination target calculation process.

  If it is determined that the circuit element 31 malfunctions, the mask layout data is corrected. The CPU 10 executes a determination target calculation process based on the corrected mask layout data, and further executes an operation verification process based on the execution result of the determination target calculation process. In this case, it is not necessary to execute the determination criterion calculation process.

  By the way, when the operation verification is performed on all the circuit elements 31, 31,..., The determination reference calculation process, the determination target calculation process, and the operation verification process are sequentially performed on one circuit element 31, and then the other circuit elements. The determination reference calculation process, the determination target calculation process, and the operation verification process are sequentially executed on the control unit 31. It should be noted that the determination criterion calculation process may be sequentially executed on each of the circuit elements 31, 31,..., The determination target calculation process may be sequentially executed, and the operation verification process may be sequentially executed.

  Regarding the determination criterion calculation process, the determination target calculation process, and the operation verification process as described above, the CPU 10 in S53 determines the allowable power supply voltage drop amount based on the relationship stored in the storage unit and the given delay change amount. It functions as a permissible power supply voltage drop amount calculation means. The CPU 10 in S56 functions as a determination unit that determines whether or not the power supply voltage drop amount related to the circuit element 31 exceeds the allowable power supply voltage drop amount obtained by the allowable power supply voltage drop amount calculation unit.

  Further, the CPU 10 in S54 functions as an allowable ground voltage drop amount calculation means for obtaining an allowable ground voltage drop amount based on the relationship stored in the storage means and a given delay change amount. Furthermore, the CPU 10 in S60 functions as an excess determination unit that determines whether or not the ground voltage drop amount related to the circuit element 31 exceeds the allowable ground voltage drop amount obtained by the allowable ground voltage drop amount calculation unit.

  The CPU 10 in S35 functions as power supply voltage drop amount calculation means for obtaining the power supply voltage drop amount related to the circuit element 31 based on the current consumption of the circuit element 31 and the resistance of the power supply wiring 32. The CPU 10 in S38 It functions as a ground voltage drop amount calculation means for obtaining a ground voltage drop amount related to the circuit element 31 based on the current consumption of 31 and the resistance of the ground wiring 33. The determining means determines whether or not the power supply voltage drop amount obtained by the power supply voltage drop amount calculating means exceeds the allowable power supply voltage drop amount. The excess determining means calculates the ground voltage drop amount. It is determined whether the ground voltage drop amount obtained by the means exceeds the allowable ground voltage drop amount.

  The CPU 10 in S22 serves as delay change amount calculation means for obtaining a delay change amount indicating a change due to a voltage drop in a delay time of a signal input to and output from the circuit element 31 based on an input signal and an output signal to the circuit element 31. Function. The storage means stores the relationship between the power supply voltage drop amount and the ground voltage drop amount related to the type of the circuit element 31 and the delay change amount calculated by the delay change amount calculation means.

The circuit operation verification device 1 as described above can accurately verify malfunction while considering the power supply voltage drop and the ground voltage drop. Further, a function ΔV (P) that is a relationship among the power supply voltage drop amount, the ground voltage drop amount, and the delay change amount related to the type of the circuit element 31 is stored in the relationship storage unit 162 and stored in the relationship storage unit 162. In order to obtain the allowable power supply voltage drop amount ΔV _DDY and the allowable ground voltage drop amount ΔV _SSY based on a certain function ΔV (P), the malfunction should be verified simply and at high speed while considering the power supply voltage drop and the ground voltage drop. Can do.

  Furthermore, when determining whether or not a circuit element malfunctions, a logic simulation is not required for timing verification, for example, so that malfunction can be verified easily and at high speed.

  Furthermore, when it is determined that the circuit element malfunctions, when the mask layout data is corrected and the circuit operation verification is performed again, or when the design constraint condition of the semiconductor integrated circuit 3 is changed, at least the determination criterion calculation process Does not need to be executed. That is, the function ΔV (P) stored in the relationship storage unit 162 can be reused without being changed. For this reason, the process required for the operation verification of the semiconductor integrated circuit 3 can be reduced. When performing operation verification on a plurality of semiconductor integrated circuits 3, 3,... With different layouts, when the types of circuit elements 31, 31,... Constituting each semiconductor integrated circuit 3 are the same, the relationship storage unit 162. The function ΔV (P) stored in can be used.

  The condition storage unit 161 and the relationship storage unit 162 may be configured to store data given from the outside. That is, the function ΔV (P) may be given.

It is a block diagram which shows the structure of the circuit operation verification apparatus which concerns on this invention. 1 is a layout diagram showing a configuration of a semiconductor integrated circuit whose operation is to be verified using a circuit operation verification apparatus according to the present invention. FIG. 3 is a circuit diagram showing a configuration of an equivalent circuit for voltage drop analysis of a semiconductor integrated circuit whose operation should be verified using the circuit operation verification apparatus according to the present invention. 1 is a circuit diagram showing a configuration of circuit elements of a semiconductor integrated circuit whose operation should be verified using a circuit operation verification apparatus according to the present invention. It is explanatory drawing which shows the delay change which concerns on the circuit element of the semiconductor integrated circuit which should perform operation verification using the circuit operation verification apparatus which concerns on this invention. It is a characteristic view which shows the relationship between the delay variation | change_quantity and the total voltage drop amount which concern on the circuit element of the semiconductor integrated circuit which should perform operation verification using the circuit operation verification apparatus based on this invention. It is a flowchart which shows the procedure of the criteria calculation process of the circuit operation verification apparatus which concerns on this invention. It is a flowchart which shows the procedure of the criteria calculation process of the circuit operation verification apparatus which concerns on this invention. It is a flowchart which shows the procedure of the determination target calculation process of the circuit operation verification apparatus which concerns on this invention. It is a flowchart which shows the procedure of the operation verification process of the circuit operation verification apparatus which concerns on this invention.

Explanation of symbols

1 Circuit operation verification device 10 CPU
162 Relationship storage unit (storage means)
2 Recording medium 3 Semiconductor integrated circuit 31 Circuit element 32 Power supply wiring 33 Ground wiring

Claims (7)

In a circuit operation verification method for verifying whether a circuit element included in a semiconductor integrated circuit malfunctions with a circuit operation verification apparatus,
Based on the power supply voltage drop amount and the ground voltage drop amount indicating the voltage drop due to each of the power supply wiring and the ground wiring of the semiconductor integrated circuit, an allowable power supply voltage drop amount satisfying the design constraint condition of the semiconductor integrated circuit is obtained,
Determining whether or not a power supply voltage drop amount indicating a voltage drop due to a power supply wiring connected to a circuit element included in the semiconductor integrated circuit exceeds an obtained allowable power supply voltage drop amount;
A circuit operation verification method, comprising: determining that the circuit element malfunctions when it is determined that the power supply voltage drop amount exceeds the allowable power supply voltage drop amount. Whether or not a circuit element included in the semiconductor integrated circuit malfunctions is provided based on a power supply voltage drop amount and a ground voltage drop amount indicating a voltage drop caused by the power supply wiring and the ground wiring respectively included in the semiconductor integrated circuit. A circuit operation verification method for verifying with a circuit operation verification device,
The power supply voltage drop amount and the ground voltage drop amount related to the same type of circuit element as the type of the circuit element included in the semiconductor integrated circuit, and the voltage of the delay time of the signal input to and output from the type of circuit element The relationship of the delay change amount indicating the change due to the descent is stored in the storage means,
Based on the relationship stored in the storage means and a given delay change amount, an allowable power supply voltage drop amount is obtained,
A circuit operation verification method, comprising: determining whether or not the power supply voltage drop amount relating to a circuit element included in the semiconductor integrated circuit exceeds the obtained allowable power supply voltage drop amount. Circuit operation verification for verifying whether or not a circuit element included in the semiconductor integrated circuit malfunctions based on a power supply voltage drop amount and a ground voltage drop amount indicating a voltage drop caused by the power supply wiring and the ground wiring respectively included in the semiconductor integrated circuit. A device,
The power supply voltage drop amount and the ground voltage drop amount related to the same type of circuit element as the type of the circuit element included in the semiconductor integrated circuit, and the voltage of the delay time of the signal input to and output from the type of circuit element Storage means for storing a relationship of a delay change amount indicating a change due to descent;
An allowable power supply voltage drop amount calculating means for obtaining an allowable power supply voltage drop amount based on the relationship stored in the storage means and a given delay change amount;
Determination means for determining whether or not the power supply voltage drop amount related to the circuit element included in the semiconductor integrated circuit is greater than the allowable power supply voltage drop amount obtained by the allowable power supply voltage drop amount calculation means. A circuit operation verification device. An allowable ground voltage drop amount calculating means for obtaining an allowable ground voltage drop amount based on the relationship stored in the storage means and the given delay variation;
The excess determination unit for determining whether or not the ground voltage drop amount related to the circuit element exceeds the allowable ground voltage drop amount obtained by the allowable ground voltage drop amount calculation unit. 4. The circuit operation verification device according to 3. Power supply voltage drop amount calculating means for obtaining the power supply voltage drop amount related to the circuit element based on the current consumption of the circuit element and the resistance of the power supply wiring;
Ground voltage drop amount calculating means for obtaining the ground voltage drop amount related to the circuit element based on the current consumption and the resistance of the ground wiring, and
The determination means determines whether or not the power supply voltage drop amount obtained by the power supply voltage drop amount calculation means exceeds the allowable power supply voltage drop amount,
5. The excess determination unit determines whether or not the ground voltage drop amount obtained by the ground voltage drop amount calculation unit exceeds the allowable ground voltage drop amount. The circuit operation verification device described. A delay change amount calculating means for obtaining a delay change amount indicating a change due to the voltage drop in a delay time of a signal input to and output from the type of circuit element based on an input signal and an output signal to the type of circuit element; Prepared,
The storage means stores the relationship between the power supply voltage drop amount and the ground voltage drop amount related to the circuit element of the type, and the delay change amount calculated by the delay change amount calculation means. The circuit operation verification apparatus according to claim 3. Let the computer verify whether or not a circuit element included in the semiconductor integrated circuit malfunctions based on a power supply voltage drop amount and a ground voltage drop amount indicating a voltage drop caused by the power supply wiring and the ground wiring of the semiconductor integrated circuit, respectively. A computer program for
The power supply voltage drop amount and the ground voltage drop amount relating to the same type of circuit element as the type of the circuit element included in the semiconductor integrated circuit, and a delay time of a signal input / output to / from the type of circuit element A step of obtaining an allowable power supply voltage drop amount based on a relationship of a delay change amount indicating a change due to the voltage drop and a given delay change amount;
And causing the computer to determine whether or not the power supply voltage drop amount relating to the circuit element included in the semiconductor integrated circuit exceeds the obtained allowable power supply voltage drop amount.

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