JPH07202000A - Lsi wiring system by parallel processing - Google Patents

Abstract

PURPOSE:To solve the wiring problems of an LSI with a high speed by a method wherein wirings are processed in parallel by using parallel computers. CONSTITUTION:Net data are received by computers and the respective computers recognize the nets of which they are in charge and determine the respective wiring regions of the nets. Then wiring routes in predetermined partial wiring regions are searched. In this case, the partial wiring routes which are allocated to the respective nets can be searched independently from the searches of the other nets. Therefore, the searches of the respective nets can be processed in parallel and independently. Then the results of the wiring processes by the computers are summerized and the existence of non-wired nets is checked. If the non-wired nets exist, the above mentioned procedure is repeated. The division and allocation processes of the second cycle is partially different from those of the first cycle and, if necessary, a basic rectangular region is expanded so as to avoid obstacles. At the same time, if the nets which are influenced by the expansion exist among the peripheral non-wired nets, a process to inform the computers in charge of those nets of the fact is added. The above mentioned process is performed at least one cycle and the elimination of the non-wired nets can be executed with a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses an LS using a plurality of computers connected by a parallel computer or a network.
The present invention relates to an LSI wiring method by parallel processing in which an I (large-scale integrated circuit) wiring problem is solved at high speed by parallel processing and LSI wiring is performed.

[0002]

2. Description of the Related Art As a wiring problem of an LSI, a set of terminals to which the constituent elements of a circuit to be wired are given the same electric potential on the chip (hereinafter referred to as a net)
Is to determine the wiring route of all nets while satisfying the electrical and physical conditions. Usually, a virtual two-dimensional lattice is set on the chip, all the wirings pass through the lattice, and this is treated as a problem of finding the wiring route of each net so that the wirings of different nets do not overlap.

The maze method is known as a typical conventional method. This starts from one terminal in the net as the starting point, starts from the grid point with that terminal, sequentially writes labels to all the grids in the writable area of the adjacent grid points, and reaches the target point. It is an algorithm that iterates or repeats until no label is attached. This method is 2
Regarding the wiring between terminals, there is a feature that if there is a route, it is always found, and that the route is guaranteed to be the shortest.

However, since the maze method is an algorithm for sequentially processing each wiring, the wiring area is wide,
Moreover, in an LSI having an enormous number of wirings, a great deal of processing time is required to complete all the wirings. In addition, if the order of nets to be routed is out of order, the number of nets that cannot be routed may increase. However, it is necessary to determine the appropriate routing order that minimizes the number of nets that cannot be routed. It is difficult to make a general guideline because it depends on the wiring conditions. Therefore, normally, when the wiring process is performed once and the wiring that cannot be wired occurs, the wiring route is manually corrected or the automatic peeling and rewiring method is used. The former can finally obtain higher quality wiring than the latter, but it is inefficient for large-scale LSI wiring, and the quality is somewhat degraded, but the latter means is usually used in practice. is there. However, for the latter as well,
However, there is a problem that the processing time becomes enormous as the scale increases.

[0005]

As described above, when the LSI wiring problem is solved by the conventional method, the wiring becomes sequential, which requires a huge amount of processing time, and the wiring order of the nets makes the wiring impossible. There is a problem that the net may increase.

The present invention has been accomplished to solve the above problems, and performs parallel wiring processing by using a parallel computer or a plurality of computers connected by a network to solve an LSI wiring problem at high speed. By L
The purpose is to provide an SI wiring system.

[0007]

According to the present invention, an LSI
A parallel processing that can obtain a high-speed and high-quality solution by dividing the wiring problem of the above into independent subproblems and solving them in parallel by each processor of a parallel computer or multiple computers connected by a network. To provide an LSI wiring system.

Further, there is provided an LSI wiring system by parallel processing capable of solving a larger-scale problem than before by using a plurality of processors. That is, the wiring area is divided into areas that can be wired independently of each other, and the processing of searching the wiring path of the net included in each area is a partial problem, and these are connected on each processor of the parallel computer or by the network. Provided is an LSI wiring system that processes independently and in parallel on a plurality of computers.

[0009]

According to the present invention, since each wiring process is handled in parallel by dividing the wiring area, a significant increase in speed can be achieved. Further, it is not necessary to set the wiring order in advance, and moreover, the wiring of higher quality than the conventional method can be obtained.

[0010]

EXAMPLE An example of the present invention will be described below.

First, a method of dividing the wiring problem into subproblems which can be independently processed by each processor or each computer will be described. Dividing into sub-problems that can be processed independently means dividing a wiring region into sub-regions that enable independent search of a wiring route. This partial area is basically a rectangular area having a net terminal as shown in FIG. That is, in FIG. 2, when 8 and 9 are terminals of the net, the basic partial area of this net is 10
It is a rectangular area shown in.

The net is basically provided as a set of two terminals, but in general, it may be provided as a set of two or more terminals. The former is called a 2-terminal net and the latter is called a multi-terminal net. All multi-terminal nets can be decomposed into two-terminal nets without loss of generality, and here, for simplicity, all nets are given as two-terminal nets. Therefore, the net data is given as a set of two-terminal grid point positions. The grid point position is
For example, one direction of the grid can be expressed as the x-axis direction, the other direction as the y-axis direction, and an appropriate position can be used as the origin, and the coordinates can be expressed in units of the grid spacing. The data of the rectangular area 10 is, for example, the minimum value, the maximum value, or the y value of the x coordinate value.
It can be expressed as a set of minimum and maximum coordinate values.

In general, the rectangular area 10 often overlaps with the adjacent nets, and the overlapped areas cannot be treated independently of each other. Therefore, this overlapping area is further divided so that it can be treated independently. The method of division depends on the positional relationship of the terminals of each net.
There are roughly two types. One is a method of monopolizing one net, and the other is a method of dividing the nets. Further, the former and the latter are further classified into two according to the monopolizing method or dividing method.

FIG. 3 shows one mode in which the overlapping area is monopolized in one area. In such an example, the net 12 entirely contained in the area 11 is made to monopolize the overlapping area 12. That is, the net is provided with the entire basic rectangular area of itself as the wiring area.

FIG. 4 shows another mode in which the overlapping area is monopolized in one area. In such an example, a net in which one terminal having the area 14 as a basic rectangular area is included in the other area 13 is made to monopolize the area where the area 13 and the area 14 overlap. In other words,
If even one terminal is included in the other area, the area overlapping the net is monopolized.

FIG. 5 shows another form in which one area is occupied by the overlapping area. In such an example, it is not unique which one of the regions 15 and 16 is used to monopolize the overlapped region, but in the case of multilayer wiring, for example, either the vertical direction or the horizontal direction is given priority for each layer. Decide. The other is left as an unrouted net and processed in the next cycle.

FIG. 6 shows a form in which the overlapping areas are further divided so that they can be handled independently. In such an example, the line 17 is divided by a straight line 19 that passes through the two intersecting points of the regions 17 and 18.

FIG. 7 shows another mode in which the overlapping areas are further divided so that they can be handled independently.
In such an example, it is divided by a straight line 22 that passes through the two opposite vertices of the two nets of the regions 20 and 21.

In this way, regarding the rectangular area, which is the basic partial wiring area of each net, the overlap with the area of the surrounding nets is examined, and the portion to be monopolized by other nets and the portion to be divided are given to each one. Exclude from the partial wiring area. In this way, the area left after the above processing is completed for all the peripheral nets overlapping the rectangular area becomes an area that can be handled independently of the wiring processing of other nets.

Since the wiring route search in the partial wiring area independent from the other obtained in this way can be processed completely independently on each processor of the parallel computer or on a plurality of computers connected by the network. High parallelism is obtained.

An LSI wiring method by parallel processing using the method of the present invention will be described with reference to the flowchart shown in FIG.

In step 1, each processor or computer obtains net data. Here, it is assumed that the net data includes data of nets to be wired, constraint conditions on the chip surface such as a wiring prohibited area, and route information of nets for which wiring is completed in the second and subsequent cycles.
In step 2, each processor or computer recognizes its own net. In step 3, each processor or computer determines its own wiring area for the net.

The above-mentioned division rule of the partial wiring area is arranged so that even if the division processing is independently performed for each net, it does not contradict each other. By using such a rule, this division processing is also performed. It can be processed in parallel and independently on a processor or a computer. In step 4, a wiring route within the partial wiring area determined in step 3 is searched. In this case, since the search of the wiring route in the partial wiring area assigned to each net can be performed independently of the search of other nets, it is possible to process the nets in parallel and independently. In step 5, the results of the wiring process in each processor or computer are totaled. In step 6, the unrouted net is examined. In step 6, if there is an unrouted net, the route of the routed net is reflected in the net data in step 7, and for the unrouted net, the procedure returns to step 1 and the same processing as above is performed. repeat. However, in the second and subsequent cycles, the division and allocation processing of the wiring area is partially different from that in the first cycle, and if necessary, the basic rectangular area is expanded so as to avoid obstacles. At the same time, if there is a net that is affected by the expansion among the unwired nets in the periphery, a process of notifying the processor or computer in charge of the net is added. If the unrouted nets are eliminated in step 6 after performing the processing from step 1 to step 5 one or more times,
The wiring process is completed.

As described above, it is also effective to make wiring processing more efficient by adding processing based on slightly different heuristics for each cycle to the processing from step 1 to step 5. Is. In addition, among unwired nets, for a net whose expansion of the basic rectangular area is insufficient in the wiring area as described above, the wiring process is terminated as an unwiring net, or
Alternatively, it is also effective to remove the already-routed nets and obtain the wiring area again with a different allocation rule.

[0025]

As described above, according to the present invention,
By dividing the LSI wiring area into sub-areas and letting these sub-areas be independently solved by multiple processors of a parallel computer or multiple computers connected by a network, the wiring problem of large-scale LSI can be accelerated. It is possible to solve, and it is not necessary to set the wiring order in advance, and high-quality wiring can be performed at high speed as compared with the conventional method.

[Brief description of drawings]

FIG. 1 is a flow chart for explaining a wiring system by parallel processing according to an embodiment of the present invention.

[Figure 2] Basic partial wiring area

FIG. 3 is a diagram showing a first example of occupying an overlapping area.

FIG. 4 is a diagram showing a second example in which an overlapping area is occupied.

FIG. 5 is a diagram showing a third example in which an overlapping area is occupied.

FIG. 6 is a diagram showing a first example of dividing an overlapping area.

FIG. 7 is a diagram showing a second example of dividing an overlapping area.

[Simple explanation of the sign]

8 ... Net terminal, 9 ... Net terminal, 10 ... Basic partial wiring area, 11 ... Net including other nets, 1
2 ... Enclosed net, 13 ... Net enclosing terminals of other nets, 14 ... Net enclosing one terminal of nets, 15 ... One net that intersects, 16 ... Other net that intersects, 17 ... One net that partially overlaps, 18
... the other net partially overlapping, 19 ... 2 of the two wiring areas
A straight line passing through two intersections, 20 ... One net including one terminal of the other net, 21 ... Another net including one terminal of the other net, 22 ... A straight line passing through two facing terminals of two nets.

Claims (3)

[Claims] 1. In an LSI wiring method for obtaining a plurality of wiring paths on a two-dimensional wiring grid, a step of dividing the wiring area for each net so that the wiring areas are independent of each other,
The net wiring process in each divided area is used as a processing unit, and these nets are distributed to a plurality of processors of a parallel computer or a plurality of computers connected by a network,
An LSI wiring method including a step of performing high-speed wiring by parallel processing. 2. The dividing step has a step of deciding to which wiring area of a net an area in which rectangular areas having the end points of a plurality of nets as vertices are overlapped is assigned according to a predetermined rule. The wiring system according to claim 1, wherein: 3. The dividing step has a step of dividing an overlapping area of rectangular areas having the endpoints of a plurality of nets as vertices and assigning the divided nets to a net according to a predetermined rule. The wiring method described in 1.