JPH0216720A - Solid phase epitaxy method - Google Patents
Solid phase epitaxy methodInfo
- Publication number
- JPH0216720A JPH0216720A JP16650288A JP16650288A JPH0216720A JP H0216720 A JPH0216720 A JP H0216720A JP 16650288 A JP16650288 A JP 16650288A JP 16650288 A JP16650288 A JP 16650288A JP H0216720 A JPH0216720 A JP H0216720A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- single crystal
- seed
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000000348 solid-phase epitaxy Methods 0.000 title 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 239000013078 crystal Substances 0.000 claims description 9
- 239000007790 solid phase Substances 0.000 claims description 9
- 238000001947 vapour-phase growth Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 238000004140 cleaning Methods 0.000 description 4
- 239000012071 phase Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 241000981595 Zoysia japonica Species 0.000 description 1
- 230000003042 antagnostic effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008710 crystal-8 Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
イ)産業上の利用分野
本発明は、SOI構造の形成における、杷は膜上へのS
i膜の固相エピタキシャル成長方法に関する。DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention is directed to the formation of an SOI structure.
This invention relates to a method for solid-phase epitaxial growth of i-films.
r:1)従来の技術
絶縁層(絶υ物の基板も含む)上に単結晶Si層を形成
したものは、5OI(S目1con onInsul
ator)構造と称され、狭い領填で容易に素子分屋が
行なえ、高集積化や高速化が可能なものとして知られて
いる。そして、従来のSi基板上に素子が作製される半
導体集積回路(IC)に比べて、特性向上が図れること
から盛んに研究開発が行なわれている〔例えばJapa
nese Journal of Applie
d Physics Vol、 26゜No、1
1.November、1987.pp−1Si6−1
822参照)。r: 1) Conventional technology The one in which a single crystal Si layer is formed on an insulating layer (including an insulating substrate) is 5OI (S 1 con on Insul).
It is known as a structure in which elements can be easily separated in a narrow area and can be highly integrated and operate at high speed. Compared to semiconductor integrated circuits (ICs) in which elements are fabricated on conventional Si substrates, R&D is actively being carried out because the characteristics can be improved [e.g.
nese Journal of Applie
d Physics Vol, 26°No, 1
1. November, 1987. pp-1Si6-1
822).
絶縁層上に単結晶Si膜を形成させるものとして、同相
エピタキシャル成長法があシ、これは、単結晶Si基板
上に、Si基板面の一部をシードとして露出させて絶縁
膜を形成し、シードと絶縁膜上に非晶質Si(以下a−
8Lと称す)膜を堆積し、600°C程度の低温でアニ
ールすることで、横方向に固相成長させて、a−fSi
膜を単結晶化させるものである。The in-phase epitaxial growth method is used to form a single-crystal Si film on an insulating layer.This method forms an insulating film on a single-crystal Si substrate by exposing a part of the Si substrate surface as a seed. and amorphous Si (hereinafter a-
A-fSi
This makes the film single-crystal.
ハ】発明が解決しようとするfs題
しかし、従来の同相エピタキシャル方法においては、シ
ードから横方向に単結晶化する距離は短く、SOI構造
として小面積のものしか得られなかった。C] fs problem to be solved by the invention However, in the conventional in-phase epitaxial method, the distance from the seed for single crystallization in the lateral direction is short, and only a small area SOI structure can be obtained.
本発明は斯様な点に渥みて為されたもので、固相エピタ
キシャル成長におけるシードからの横方向への単結晶成
長距離を伸ばし、より大面積のSOI構造を形成しうる
固相エピタキシャル成長方法を提供するものである。The present invention has been made with these points in mind, and provides a solid-phase epitaxial growth method that can extend the lateral single crystal growth distance from a seed in solid-phase epitaxial growth and form an SOI structure with a larger area. It is something to do.
二) 課題を解決するための手段
本発明は、絶縁膜が開孔されて露出されるシードの形状
を幅が50μm以上のライン形状とする固相エビタΦシ
ャル成長方法であり、また、基板上へのa−fSiの堆
積を520°C乃至550℃の成長温度で減圧気相成長
によシ行う固相エピタキシャル成長方法である。2) Means for Solving the Problems The present invention is a solid-phase epitaxial growth method in which a hole is opened in an insulating film and the exposed seed has a line shape with a width of 50 μm or more. This is a solid phase epitaxial growth method in which a-fSi is deposited on the substrate by low pressure vapor phase growth at a growth temperature of 520°C to 550°C.
ホ)作 用
シードの形状を幅50μm以上のライン形状とすること
によシ、シードとして露出している単結晶Si面の清浄
化が良好に行なわれて、a−8量膜の同相エピタキシャ
ル成長距離が伸びる。また、減圧気相成長によるa−S
i膜の堆積を、520℃乃至550°Cの成長温度で行
うことによってa−Si膜として良質の膜が形成され、
a −Si膜の同相エピタキシャル成長距離が伸びる。E) Effect: By making the shape of the seed into a line shape with a width of 50 μm or more, the single-crystal Si surface exposed as the seed can be well cleaned, and the in-phase epitaxial growth distance of the a-8 mass film can be improved. grows. In addition, a-S by reduced pressure vapor phase growth
By depositing the i film at a growth temperature of 520°C to 550°C, a high quality a-Si film is formed.
The in-phase epitaxial growth distance of the a-Si film increases.
勺実施例 第1図人乃至りは本発明一実施例の概略工程図を示す。Example FIG. 1 shows a schematic process diagram of an embodiment of the present invention.
本実施例では単結晶Si基台として、単結晶Si基板を
用いているが、基板上に形成された単結晶Si膜を用い
ても良い。In this embodiment, a single crystal Si substrate is used as the single crystal Si base, but a single crystal Si film formed on the substrate may also be used.
11)は(100)面を主面とする単結晶Si基台とし
ての単結晶Si基板で、その表面に絶縁膜として膜厚1
2膜程のS ioz膜(21をCVD(化学気相成長)
法によシ堆積させる(第1図人)。単結晶Si基板(1
1の<100>方向に2イン形状の開孔部(2イを、S
i02膜(2)にフォトリングラフィ技術によシバター
ン形成する(同図B)。このとき、開孔部(21は、第
2図に示す様に、開孔部(グ1の形成によシ単結晶Si
基板tlj面が露出したシード部+11の形状が、その
幅dが50μm以上であるライン形状となるように形成
される。11) is a single-crystal Si substrate as a single-crystal Si base with the (100) plane as the main surface, and an insulating film on the surface with a thickness of 1
Approximately 2 SiOZ films (21 are CVD (chemical vapor deposition)
Deposit it by law (Figure 1 person). Single crystal Si substrate (1
2-inch opening in the <100> direction of 1 (2-inch, S
A shiba pattern is formed on the i02 film (2) by photolithography technology (FIG. B). At this time, as shown in FIG.
The shape of the seed portion +11 in which the substrate tlj surface is exposed is formed in a line shape with a width d of 50 μm or more.
次に表面全面上Ka−Si膜を形成するが、まず、a−
Siの形成面、特に、シード部(6表面の清浄化を行う
。シード部uf面の清浄に先立ち、図示しない減圧CV
D装置の反応管内は、基板保持具(サセプタ〕と共に清
浄化しておく。即ち、反応管内を8 X 10−’To
rr以下の真空状態くし、その後600℃まで昇温して
1 x 10−’Torr以下の真空度に保持した状態
で、 A rガスを120SCCMの流量で導入し、R
F発振器により出力50W程度のRFを印加してArプ
ラズマを発生し、基板保持具に5QQVの負電圧を印加
してArプラズマによる反応管内と基板保持具のスパッ
タを行う。そして、30分間スパッタをした後、真空度
が5X 10−’Torr以上にした状態で室温まで降
温しておく。Next, a Ka-Si film is formed on the entire surface.
The Si forming surface, especially the seed part (6 surface), is cleaned. Prior to cleaning the seed part uf surface, a vacuum CV (not shown)
The inside of the reaction tube of apparatus D is cleaned together with the substrate holder (susceptor).In other words, the inside of the reaction tube is cleaned with 8 x 10-'To
After creating a vacuum state below RR, the temperature was raised to 600°C and maintained at a vacuum level below 1 x 10-' Torr, Ar gas was introduced at a flow rate of 120 SCCM, and R
Ar plasma is generated by applying RF with an output of about 50 W using an F oscillator, and a negative voltage of 5QQV is applied to the substrate holder to perform sputtering on the inside of the reaction tube and the substrate holder using the Ar plasma. After sputtering for 30 minutes, the temperature is lowered to room temperature while the degree of vacuum is 5×10 Torr or higher.
さて、斯様に清浄化のされている減圧CVD装置の反ろ
管(図示せず)内にSi0z膜(2)が選択的に形成さ
れた基板11)を設置する。そして、基板温度を550
°C迄昇温し、保持した状態で、前述と同様に反応室内
にAtガスを1208CCMの流量で導入し、RF発振
器を用いて1五56MHzのRFを印加することにより
Arプラズマを発生させる。この時のRF小出力50膜
程度とする。Now, the substrate 11) on which the Si0z film (2) has been selectively formed is placed inside the convection tube (not shown) of the vacuum CVD apparatus that has been cleaned in this manner. Then, set the substrate temperature to 550
While the temperature is raised to and maintained at °C, At gas is introduced into the reaction chamber at a flow rate of 1208 CCM as described above, and RF of 1556 MHz is applied using an RF oscillator to generate Ar plasma. The low RF output at this time is about 50 films.
そして基板に500v程度の負電圧を印加すると、Ar
+イオンが基板表面に衝突し、基板がスパッタされるこ
とにより、その表面が清浄化される。清浄化に要するス
パッタ時間は30分程度である。Then, when a negative voltage of about 500V is applied to the substrate, Ar
The + ions collide with the substrate surface and the substrate is sputtered, thereby cleaning the surface. The sputtering time required for cleaning is about 30 minutes.
基板面の清浄が終了したらArガスの供給を停止し、基
板温度を530°Cまで降温し、保持する。When cleaning of the substrate surface is completed, the supply of Ar gas is stopped, and the substrate temperature is lowered to 530° C. and maintained.
その後、SiH4ガスを流量50SCCM、SiH4分
圧10’pOrrで反応管内に供給して、a−84膜の
気相成長を行い、シード部(6及びSiQz膜(2)上
にa−Si膜(3)を堆積させる(第1図C]。Thereafter, SiH4 gas was supplied into the reaction tube at a flow rate of 50 SCCM and a SiH4 partial pressure of 10'pOrr to perform vapor phase growth of an a-84 film, and an a-Si film ( 3) is deposited (Fig. 1C).
このときのa−Si膜(3)の膜厚に15μm (士α
2μm程度]とする。At this time, the film thickness of the a-Si film (3) was 15 μm (
approximately 2 μm].
最後に、基板温度が600°Cに設定保持されたN2雰
囲気(大気圧)内で、12時間アニール処理を行う。す
ると、シード部(1丁の結晶方位を継承しつつ、横方向
に固相エピタキシャル成長がされ、a−Si膜(3)が
単結晶化して単結晶8に膜(3躇なる(第1図D)。Finally, an annealing process is performed for 12 hours in a N2 atmosphere (atmospheric pressure) where the substrate temperature is set and maintained at 600°C. Then, solid-phase epitaxial growth is performed in the lateral direction while inheriting the crystal orientation of the seed part (1), and the a-Si film (3) becomes a single crystal, forming a single crystal 8 (3) (Fig. 1D). ).
第6図に上記実施例において、シード部(開孔部)の幅
dだけを変化させた場合のライン形状に形成されるシー
ド部uf (開孔部(21)の幅dと、a−Si膜(3
)が単結晶化する横方向の成長距離との関係を示す。第
5図かられかる様に、シード部(開孔部〕の@dが50
μm以上では横方向成長距離は安定して良好であるが、
50μvz 以下になると横方向成長距離は極端に悪く
なる。これは、シード部の幅dを50μm以上とするこ
とによシ、シード部+xfの表面の清浄化が良好に行わ
れ、エピタキシャル成長を阻害する粒界の発生を抑える
如く、アニール温度に達したa−Si膜が時間を置くこ
となく順次単結晶化(エピタキシャル成長)されるため
と考えられる。また、シード面の結晶方位を継承した成
長(エピタキシャル成長)を阻害するように働く開孔部
(2Sにおける絶縁膜(2)のエツジ部分からの残留応
力が、シード部の幅d′?r、50μm以上とすること
によシ、a−si膜に対してあまり影響を及ぼさなくな
るからである。FIG. 6 shows the seed portion uf (the width d of the opening (21) and the a-Si Membrane (3
) shows the relationship with the lateral growth distance for single crystallization. As shown in Figure 5, @d of the seed part (opening part) is 50
Above μm, the lateral growth distance is stable and good, but
When it becomes less than 50 μvz, the lateral growth distance becomes extremely poor. By setting the width d of the seed part to 50 μm or more, the surface of the seed part + This is thought to be because the -Si film is successively single-crystalized (epitaxially grown) without any time delay. In addition, the residual stress from the edge portion of the insulating film (2) in the opening (2S) that acts to inhibit growth (epitaxial growth) that inherits the crystal orientation of the seed surface is caused by the width of the seed portion d'? This is because by doing so, the a-si film will not be affected much.
さて、第4図は、シード部(1fの幅dを500μmと
し、基板温度(成長温度)を変化させた場仕の、a−S
i膜13)が単結晶化する横方向の成長距離を示すもの
である。第4図かられかるように、基板温度(成長温度
)を上げるにつれて、徐々に横方向の成長距離は短くな
っている。基板温度が高ければ、堆積されるa−8t膜
中の多、拮晶部分が増加し、この多結晶部分がアニール
時にエピタキシャル成長を阻害する粒界として成長する
。つtシ、非晶質な膜として多結晶部分のより少ない良
質なa−Si膜を形成することにより、横方向の成長距
離が伸び、そのためには、基板温度(成長温度)を55
0℃以下にすれば良いことになる。Now, FIG. 4 shows the a-S
It shows the lateral growth distance at which the i-film 13) becomes a single crystal. As can be seen from FIG. 4, as the substrate temperature (growth temperature) increases, the lateral growth distance gradually becomes shorter. If the substrate temperature is high, the polycrystalline and antagonistic portions in the deposited A-8T film increase, and these polycrystalline portions grow as grain boundaries that inhibit epitaxial growth during annealing. However, by forming a high-quality a-Si film with fewer polycrystalline parts as an amorphous film, the lateral growth distance can be increased.
It will be fine if the temperature is below 0°C.
ただし、基板温度(成長温度)が520℃より低くくな
ると、a−Si膜の堆積がほとんどされなくなる(堆積
速度が極端に遅くなる)ため、基板温度(成長温度)と
して520℃以上550℃以下の温度でa−Si膜を形
成すれば良質のa−Si膜が得られる。However, if the substrate temperature (growth temperature) becomes lower than 520°C, the a-Si film will hardly be deposited (the deposition rate becomes extremely slow), so the substrate temperature (growth temperature) should be 520°C or more and 550°C or less. A high quality a-Si film can be obtained by forming the a-Si film at a temperature of .
ト)発明の効果
本発明は以上の説明から明らかなり口く、シードのため
の開孔部をその幅が50μm以上のライン形状とするこ
とで、あるいは、晶−Si膜を成長温度520℃乃至5
50°Cの減王CVDで形成することにより、エピタキ
シャル成長する横方向の成長距離を伸ばすことができる
。従って、よシ大きな面積のSOI構造の形成が可能と
なる。g) Effects of the invention It is clear from the above description that the present invention can be achieved by forming the opening for the seed into a line shape with a width of 50 μm or more, or by growing the crystal-Si film at a growth temperature of 520°C or more. 5
By forming the layer by the reduced-irradiation CVD at 50° C., the lateral growth distance for epitaxial growth can be extended. Therefore, it is possible to form an SOI structure with a much larger area.
第1図、へ乃至りは本発明一実施例の概略工程図、第2
図は開孔部の形状を示す上面図、第5図は開孔部の幅と
横方向成長距離の関係を示す図、第4図は成長温度と横
方向成長距離の関係を示す因である。
(1)・・・単結晶5
(2)・・・Si02膜
(3)・・・a−Si膜
i基板 (11・・・シード部
(絶縁膜)(2丁・・・開孔部
(3S・・・単結晶Si膜Fig. 1 is a schematic process diagram of an embodiment of the present invention;
The figure is a top view showing the shape of the opening, Figure 5 is a diagram showing the relationship between the width of the opening and the lateral growth distance, and Figure 4 is the factor showing the relationship between the growth temperature and the lateral growth distance. . (1)...Single crystal 5 (2)...Si02 film (3)...a-Si film i-substrate (11...Seed part (insulating film) (2 pieces...Opening part ( 3S...Single crystal Si film
Claims (2)
Si基台表面を露出させる開孔部を前記絶縁膜に選択的
に形成し、前記単結晶Si基台及び絶縁膜上に非晶質S
i膜を形成し、該非晶質Si膜をアニール処理して単結
晶化名せる固相エピタキシャル成長方法において、 前記開孔部は幅が50μm以上のライン形状であること
を特徴とする固相エピタキシヤル成長方法。(1) Forming an insulating film on a single crystal Si base, selectively forming an opening in the insulating film to expose the surface of the single crystal Si base, and forming an opening on the single crystal Si base and the insulating film. amorphous S
A solid phase epitaxial growth method for forming an i-film and annealing the amorphous Si film to form a single crystal, characterized in that the opening has a line shape with a width of 50 μm or more. Method.
Si基台表面を露出させる開孔部を前記絶縁膜に選択的
に形成し、前記単結晶Si基台及び絶縁膜上に非晶質S
i膜を形成し、該非晶質Si膜をアニール処理して単結
晶化させる固相エピタキシャル成長方法において、 前記非晶質Si膜は成長温度を520℃乃至530℃と
する減圧気相成長により形成されることを特徴とする固
相エピタキシヤル成長方法。(2) Forming an insulating film on the single crystal Si base, selectively forming an opening in the insulating film that exposes the surface of the single crystal Si base, and forming an opening on the single crystal Si base and the insulating film. amorphous S
In a solid-phase epitaxial growth method in which an i film is formed and the amorphous Si film is annealed to become a single crystal, the amorphous Si film is formed by low pressure vapor phase growth at a growth temperature of 520°C to 530°C. A solid phase epitaxial growth method characterized by:
Priority Applications (1)
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JP16650288A JPH0216720A (en) | 1988-07-04 | 1988-07-04 | Solid phase epitaxy method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP16650288A JPH0216720A (en) | 1988-07-04 | 1988-07-04 | Solid phase epitaxy method |
Publications (1)
Publication Number | Publication Date |
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JPH0216720A true JPH0216720A (en) | 1990-01-19 |
Family
ID=15832549
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5318928A (en) * | 1991-11-11 | 1994-06-07 | Leybold Aktiengesellschaft | Method for the surface passivation of sensors using an in situ sputter cleaning step prior to passivation film deposition |
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JPS60246621A (en) * | 1984-05-22 | 1985-12-06 | Agency Of Ind Science & Technol | Manufacture of semiconductor crystal layer |
JPS61201415A (en) * | 1985-03-02 | 1986-09-06 | Agency Of Ind Science & Technol | Manufacture of semiconductor single crystal layer |
JPS6449214A (en) * | 1987-08-20 | 1989-02-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH01270310A (en) * | 1988-04-22 | 1989-10-27 | Seiko Epson Corp | Manufacture of semiconductor |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6057610A (en) * | 1983-09-08 | 1985-04-03 | Matsushita Electric Ind Co Ltd | Fabrication of single crystal thin film |
JPS60246621A (en) * | 1984-05-22 | 1985-12-06 | Agency Of Ind Science & Technol | Manufacture of semiconductor crystal layer |
JPS61201415A (en) * | 1985-03-02 | 1986-09-06 | Agency Of Ind Science & Technol | Manufacture of semiconductor single crystal layer |
JPS6449214A (en) * | 1987-08-20 | 1989-02-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH01270310A (en) * | 1988-04-22 | 1989-10-27 | Seiko Epson Corp | Manufacture of semiconductor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5318928A (en) * | 1991-11-11 | 1994-06-07 | Leybold Aktiengesellschaft | Method for the surface passivation of sensors using an in situ sputter cleaning step prior to passivation film deposition |
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