JPH02208920A - Soi structure forming method - Google Patents
Soi structure forming methodInfo
- Publication number
- JPH02208920A JPH02208920A JP3062389A JP3062389A JPH02208920A JP H02208920 A JPH02208920 A JP H02208920A JP 3062389 A JP3062389 A JP 3062389A JP 3062389 A JP3062389 A JP 3062389A JP H02208920 A JPH02208920 A JP H02208920A
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- substrate
- doped
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000007790 solid phase Substances 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 23
- 239000013078 crystal Substances 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000012071 phase Substances 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
イ)産業上の利用分野
本発明はS Ol (Silicon on In5u
lator)91造の形成方法に関し、特に同相成長法
によりSi膜を形成するものに関する。[Detailed Description of the Invention] A) Industrial Field of Application The present invention is directed to silicon on
The present invention relates to a method of forming a Si film using an in-phase growth method.
口)従来の技術
絶縁層(絶縁物の基板も含む)上に単結晶S1層を形成
したものは、SOI構造と称され、狭い領域で容易に素
子分離が行なえ、高集積化や高速化がiir#、ならの
として知られている。そして、従来のSi基板上に素子
が作成される半導体集積回路(IC)に比べて、特性向
上が図られることから盛んに研究開発が行なわれている
。(Example) Conventional technology A structure in which a single crystal S1 layer is formed on an insulating layer (including an insulating substrate) is called an SOI structure, which allows for easy element isolation in a narrow area and allows for higher integration and higher speed. iir#, also known as nanano. Furthermore, research and development are being actively conducted on semiconductor integrated circuits (ICs) because they offer improved characteristics compared to conventional semiconductor integrated circuits (ICs) in which elements are fabricated on a Si substrate.
絶縁層上に単結晶Si膜を形成させるものとして、同相
成長法があり、これは、単結晶Si基板劃側に、Si基
板面の一部をシードとして絶縁膜上に露出させて絶縁膜
を形成し、シードと絶縁膜上に非晶質Si(以下a−5
iと称す)膜を堆積し、600 ’C程度の低温でアニ
ールすることで、横ノi向に同相成長させてa−3i膜
を単結晶化させる乙のである。There is an in-phase growth method to form a single crystal Si film on an insulating layer, and this method involves growing an insulating film on the side of a single crystal Si substrate by exposing a part of the Si substrate surface onto the insulating film as a seed. Amorphous Si (hereinafter a-5) is formed on the seed and insulating film.
By depositing a film (referred to as i) and annealing it at a low temperature of about 600'C, the a-3i film is made into a single crystal by growing in phase in the lateral direction of i.
固相成長における横方向の成長距離を伸ばす方法として
、絶縁膜上のa−3i膜にP+イオンを高濃度に注入し
てから、アニール処理を行なうも−のがある(Exte
nded Abstracts of the 16t
h Co−nference on 5olid 5t
ate Devices and Materials
、 Kobe、 1984. I)p、 507−51
0参照)。One way to extend the lateral growth distance in solid phase growth is to implant P+ ions at a high concentration into the a-3i film on the insulating film and then perform an annealing process (Exte
Abstracts of the 16t
h Conference on 5olid 5t
ateDevices and Materials
, Kobe, 1984. I) p, 507-51
(see 0).
ハ)5!明が解決しようとする課題
しかし、横方向の成長距離を伸ばすために、P4イオン
を3 X 10”an−”という高濃度にドーピングす
るので、固相成長した単結晶Si膜中の不純物(P)濃
度が非常に高くなってしまい、この固相成長した単結晶
5iill上での半導体素子の作成は困難であった。c) 5! However, in order to increase the lateral growth distance, P4 ions are doped at a high concentration of 3 x 10"an-", so the impurity (P) in the solid phase grown single crystal Si film is ) concentration became extremely high, making it difficult to fabricate a semiconductor device on this solid-phase grown single crystal 5iill.
また、Pをドーピングして固相成長させた単結晶Si膜
上に、基板温度800℃ぐらいで、単結晶Si膜をエピ
タキシャル成長させて、不純物濃度の低いSi膜を形成
することが考えられているが、エピタキシャル成長中の
オートドーピングや素ト作成のプロセス中の固相拡散に
より、エピタキシャル成長させたSi膜の表面の不純物
濃度はI X IQ”cm−’以上となってしまい、や
はり、半導1本素子の作成には不適当であった。It is also being considered to epitaxially grow a single crystal Si film on a solid-phase grown single crystal Si film doped with P at a substrate temperature of about 800°C to form a Si film with a low impurity concentration. However, due to auto-doping during epitaxial growth and solid-phase diffusion during the process of forming a bare metal, the impurity concentration on the surface of the epitaxially grown Si film exceeds I x IQ cm-', and as expected, one semiconductor It was unsuitable for making devices.
ニフ課題を解決するための手段
本発明は、単結晶Si基台上に該単結晶Si基台の一部
表面が露出する開孔部を有する絶縁層を形成する工程と
、該開孔部において露出する単結晶Si基台表面及び絶
縁層上にPをドーピングした第1のa−3i膜を形成す
る工程と、該第1のa −S i H上に不純物をドー
ピングしない第2の*−8i膜を形成する工程と、第1
のa−5i膜と第2のa−5i膜をアニールして同相成
長させるIl程とを備えるSOttlI造の形成方法で
ある。Means for Solving the Problems The present invention provides a step of forming an insulating layer on a single crystal Si base having an opening through which a part of the surface of the single crystal Si base is exposed; A step of forming a first a-3i film doped with P on the exposed surface of the single crystal Si base and the insulating layer, and a second *-3i film doped with no impurity on the first a-S i H. 8i film forming step and the first
This is a method for forming a SOttlI structure, which comprises an Il step in which a second a-5i film and a second a-5i film are annealed and grown in the same phase.
ホ)作用
■〕をドーピングした第1のa−Si膜上に更に不純物
のドーピングをしていない第2のa−Si膜を形成し、
これらa−3i膜をアニールして固Fll成長させると
、単結晶Si基台の結晶方位を継承して第1のa−3i
膜が固相成長し、次いで第2のa−8i膜が固相成長す
る。固相成長は比較的低温のプロセスであるので、第2
のa−5i膜・\不純物のオートドーピングは起こり難
く、Pドープによる横方向の成長距離の伸長を図った上
で1表面の不純物濃度の低い単結晶Si膜が形成される
。e) Forming a second a-Si film not doped with impurities on the first a-Si film doped with action (2);
When these a-3i films are annealed and grown as solid Flls, they inherit the crystal orientation of the single-crystal Si base and become the first a-3i films.
The film is grown in solid phase and then a second a-8i film is grown in solid phase. Since solid-phase growth is a relatively low-temperature process, the second
Autodoping of impurities in the a-5i film is difficult to occur, and a single crystal Si film with a low impurity concentration on one surface is formed by increasing the lateral growth distance by P doping.
へ)実施例
第1図A乃至Eに本発明の第1の実施例の概略l−稈図
を示す。尚、本実施例では単結晶Si基基台上て、単結
晶Si基板を用いているが、基板上に形成された単結晶
Si膜を用いてもよい。f) Embodiment FIGS. 1A to 1E show schematic diagrams of a first embodiment of the present invention. In this embodiment, a single-crystal Si substrate is used on a single-crystal Si base, but a single-crystal Si film formed on the substrate may also be used.
(1)は(100)面を主面とする単結晶Si店台とし
ての単結晶Si基板で、その表面に絶縁11りへとして
膜厚1000人程のS i O*膜(2)をCVIJ法
によって堆積させる(第1図A) (S i Os膜
は、81基板を直接熱酸化して形成してもよい)。(1) is a single-crystal Si substrate with a (100) plane as the main surface, and a SiO* film (2) with a thickness of about 1000 layers is coated by CVIJ on its surface as an insulating layer. (The SiOs film may be formed by direct thermal oxidation of the 81 substrate.) (FIG. 1A).
そして、単結晶81基板(1)の<100>方向にスト
ライプ形状の開孔部(2゛)を、Sin。Then, stripe-shaped openings (2゛) are formed in the <100> direction of the single crystal 81 substrate (1).
11’7. (2)にフォトリソグラフィ技術によりパ
ターン形成する(第1図B)。11'7. (2) A pattern is formed using photolithography technology (FIG. 1B).
次に表面全体にa−5i膜をCVD法により形成する。Next, an a-5i film is formed over the entire surface by CVD.
まず、a−5i膜の形成面、特に、開孔部(2°)の部
分で露出している単結晶Si基板rt)部分(即ちシー
ド、以下シード(1′)という)の表面の清浄化を行な
う。図示しない減圧CVD装置内に基板を設置して、1
0−’T orr台の真空ドで基板温度を約550℃に
昇温し、保持した状態で、反応室内にArガスを導入(
流量150cc7 n+in、 A r分圧65mT
orr) L、RF発振器を用いて13.56M Hz
のRFを印加することによりArプラズマを発生させる
。このときのRF高出力5 (l W(乃至70W)程
度とする。そして、基板に50〜100V程度の負電圧
を印して、Ar+イオンを基(な表面に衝突させてスパ
ッタ清浄を行なう。清浄fヒに要するスパッタ時間は5
分程度である。First, cleaning the surface on which the a-5i film is formed, especially the surface of the single crystal Si substrate rt) exposed at the opening (2°) (i.e., seed, hereinafter referred to as seed (1')). Do this. The substrate is installed in a low pressure CVD apparatus (not shown), and 1
The substrate temperature was raised to approximately 550°C in a vacuum chamber on a 0-'T orr stage, and while the temperature was maintained, Ar gas was introduced into the reaction chamber (
Flow rate 150cc7 n+in, Ar partial pressure 65mT
orr) L, 13.56 MHz using RF oscillator
Ar plasma is generated by applying RF. The RF high output at this time is about 5 (1 W) (70 W). Then, a negative voltage of about 50 to 100 V is applied to the substrate to cause Ar+ ions to collide with the surface to perform sputter cleaning. The sputtering time required for cleaning is 5
It takes about a minute.
Ar+イオンによる清浄化が終了した時点で、t’r
rガス、RF高出力バイアス印加を停止し、Sl[1,
ガス流ffi200secm、窒素をキャリアガスとす
る5%のPH,ガス40secmを流して(全体の真空
1兜は5〜10Torr) 、Pをドーピングした第1
のa −S i膜(3)の堆積を行なう(第1図C)。When cleaning with Ar+ ions is completed, t'r
r gas, RF high power bias application is stopped, and Sl[1,
The P-doped first
The a-Si film (3) is deposited (FIG. 1C).
このときの基板温度は550℃に保持された状態で、堆
積速度約100人/minで膜厚約5000人堆積させ
る。At this time, the substrate temperature is maintained at 550° C., and a film thickness of about 5000 layers is deposited at a deposition rate of about 100 layers/min.
第1のa−3i膜(3)を約5000人形成したら、P
H,ガスの供給を停止し、SiH,ガス200s(・c
fflだけを流して、不純物をドーピングしない(ノン
ドープ)第2のa−5illli(4)を第1のa−5
i膜(3)上に堆積させる(第1図D)。After forming the first a-3i film (3) for about 5,000 people, P
Stop the supply of H, gas, and apply SiH, gas for 200 s (・c
By flowing only ffl, the second a-5 illi (4) which is not doped with impurities (non-doped) is connected to the first a-5
i-film (3) (FIG. 1D).
このときの基板温度は550℃に保持したままで、If
f−A速度約250人/minで、所望のデバイス形成
がuf能な厚さ、例えば約5000人堆積させる。At this time, the substrate temperature was maintained at 550°C, and If
At an f-A rate of about 250 layers/min, a thickness of about 5000 layers is deposited to form the desired device.
第2のa−8i膜(4)の形成が終わったら、5it−
1,ガスの供給を停止し、窒素ガスのみを11z’mi
nで供給して窒素雰囲気にし、基板温度を6)1)℃に
昇温、保持して12時間アニール処理を行な′2 。After the formation of the second a-8i film (4), the 5it-
1. Stop the gas supply and supply only nitrogen gas to 11z'mi.
The substrate temperature was raised to 6)1)°C and held for 12 hours for annealing.'2
このアニール処理により、先ず、シード(1′)の結晶
方位(単結晶81基板(1)の結晶方位)を継承して第
1のa−Si膜(3)が固相成長して+B結結晶S模膜
3°)となる。第1のa−5i膜(3)はPがドーピン
グされているので、横方向の成長距離が長く、広い面積
に亙って単結晶S嘆(3°)が同相成長する。次いで固
相成長した単結晶Si膜(3′)をシードとして第2の
a−8illli(4)が固相成長し、単結晶Si膜(
3)とほぼ同じ広さの単結晶Si膜(4°)が形成され
る(第1図E)。Through this annealing treatment, first, the first a-Si film (3) inherits the crystal orientation of the seed (1') (the crystal orientation of the single crystal 81 substrate (1)) and grows in a solid phase to form +B crystals. S model 3°). Since the first a-5i film (3) is doped with P, the lateral growth distance is long, and the single crystal S (3°) grows in phase over a wide area. Next, a second a-8illi (4) is grown in solid phase using the solid phase grown single crystal Si film (3') as a seed, and the single crystal Si film (3') is then grown in solid phase.
A single crystal Si film (4°) having approximately the same width as 3) is formed (FIG. 1E).
固相成長では、基板温度は600℃程度なので、単結晶
Si膜(3’)(第1のa−5i膜)から単結晶Si膜
(4″)への不純物のドーピングは余り起こらない。こ
のため、単結晶Si膜(4°)は不純物濃度の低いもの
となる。In solid phase growth, since the substrate temperature is about 600°C, impurity doping from the single crystal Si film (3') (first a-5i film) to the single crystal Si film (4'') does not occur much. Therefore, the single crystal Si film (4°) has a low impurity concentration.
ト)発明の効果
本発明は、以上の説明から明らかな如く、Pをドーピン
グした第1のa−5i膜上に不純物をドーピングしない
第2のa−3r膜を形成し、アニール処理を施すことで
、Pドープによりa−Si膜模の横方向の成長距離を伸
ばし、大面積の単結晶Si膜を得た上で 不純物濃度の
低い単結晶Sr膜が得られる。そして、半導体素子の作
成に適したSol構造の基板が提供でき、半導体集積回
路における高集積化や特性の向上に寄与できる。g) Effects of the Invention As is clear from the above description, the present invention is to form a second a-3r film not doped with impurities on a first a-5i film doped with P, and then perform an annealing treatment. By doping with P, the lateral growth distance of the a-Si film model is extended, and a single crystal Si film with a large area is obtained, and a single crystal Sr film with a low impurity concentration is obtained. Further, it is possible to provide a substrate with a Sol structure suitable for manufacturing semiconductor elements, and it can contribute to higher integration and improved characteristics in semiconductor integrated circuits.
第1図A乃至Eは本発明の一実施例の工程説明図である
。
(1)・・・単結晶Si基板(単結晶Si基台)(l゛
)・・・シード、(2)・・・Sin、膜(絶縁11・
λ)、(2°)・・・開孔部、(3)・・・第1のa−
51膜、(3゛)・・・単結晶Si膜、(4)・・・第
2のa−3i膜、(4’)・−単結晶Si膜出出願人三
洋を機株式会社
代理人 弁理士 西野卓嗣 外2名FIGS. 1A to 1E are process explanatory diagrams of an embodiment of the present invention. (1)...Single crystal Si substrate (single crystal Si base) (l゛)...Seed, (2)...Sin, film (insulation 11.
λ), (2°)...opening part, (3)...first a-
51 film, (3゛)...Single crystal Si film, (4)...Second a-3i film, (4')...Single crystal Si film Applicant Sanyo Oki Co., Ltd. Representative Patent attorney Master Takuji Nishino and 2 others
Claims (1)
が露出する開孔部を有する絶縁層を形成する工程と、該
開孔部において露出する単結晶Si基台表面及び絶縁層
上にPをドーピングした第1の非晶質Si膜を形成する
工程と、該第1の非晶質Si膜上に不純物をドーピング
しない第2の非晶質Si膜を形成する工程と、第1の非
晶質Si膜と第2の非晶質Si膜をアニールして固相成
長させる工程とを備えることを特徴とするSOI構造の
形成方法。(1) Forming an insulating layer on a single-crystal Si base having an opening through which a part of the surface of the single-crystal Si base is exposed; a step of forming a first amorphous Si film doped with P on the insulating layer; a step of forming a second amorphous Si film not doped with impurities on the first amorphous Si film; . A method for forming an SOI structure, comprising the steps of annealing a first amorphous Si film and a second amorphous Si film to grow them in a solid phase.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3062389A JPH02208920A (en) | 1989-02-08 | 1989-02-08 | Soi structure forming method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3062389A JPH02208920A (en) | 1989-02-08 | 1989-02-08 | Soi structure forming method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02208920A true JPH02208920A (en) | 1990-08-20 |
Family
ID=12308985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3062389A Pending JPH02208920A (en) | 1989-02-08 | 1989-02-08 | Soi structure forming method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02208920A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Method of manufacturing semiconductor device |
JP2015115435A (en) * | 2013-12-11 | 2015-06-22 | 東京エレクトロン株式会社 | Method for crystallization of amorphous silicon, method for forming crystallized silicon film, method for manufacturing semiconductor device and apparatus for film formation |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60245211A (en) * | 1984-05-21 | 1985-12-05 | Oki Electric Ind Co Ltd | Formation of soi structure |
-
1989
- 1989-02-08 JP JP3062389A patent/JPH02208920A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60245211A (en) * | 1984-05-21 | 1985-12-05 | Oki Electric Ind Co Ltd | Formation of soi structure |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Method of manufacturing semiconductor device |
JP2015115435A (en) * | 2013-12-11 | 2015-06-22 | 東京エレクトロン株式会社 | Method for crystallization of amorphous silicon, method for forming crystallized silicon film, method for manufacturing semiconductor device and apparatus for film formation |
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