JPS61201415A - Manufacture of semiconductor single crystal layer - Google Patents

Manufacture of semiconductor single crystal layer

Info

Publication number
JPS61201415A
JPS61201415A JP60040324A JP4032485A JPS61201415A JP S61201415 A JPS61201415 A JP S61201415A JP 60040324 A JP60040324 A JP 60040324A JP 4032485 A JP4032485 A JP 4032485A JP S61201415 A JPS61201415 A JP S61201415A
Authority
JP
Japan
Prior art keywords
single crystal
crystal layer
film
semiconductor
spot diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60040324A
Other languages
Japanese (ja)
Other versions
JPH0236055B2 (en
Inventor
Toshihiko Hamazaki
浜崎　利彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60040324A priority Critical patent/JPS61201415A/en
Publication of JPS61201415A publication Critical patent/JPS61201415A/en
Publication of JPH0236055B2 publication Critical patent/JPH0236055B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To solidify a melted part of a semiconductor film from the circumference of the melted domain to the central part in order to make a high quality semiconductor single crystal layer of a large area grow by a method wherein a spot diameter of an energy beam is gradually reduced instead of scanning the beam. CONSTITUTION:A polycrystalline silicon film 24 is heated and melted by an electron beam with a spot diameter of 1mm. The spot diameter of the electron beam 12 is gradually reduced and the melted silicon film 24 is solidified from the circumference to the central part to be converted into a single crystal silicon film. The sport diameter of the electron beam 12 is larger than that of a seed part 23 at first and then is reduced gradually with a progress of annealing time. The electron beam intensity is also reduced along with the reduction of the spot diameter so as to keep the beam current density at the irradiated part constant. With this constitution, a uniform single crystal layer 24' of 500mum squar surrounded by the seed part 23 can be obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、絶縁膜上に薄膜状の半導体単結晶層を製造す
る方法に係わり、特にビームアニール法を利用した半導
体単結晶層の製造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing a thin semiconductor single crystal layer on an insulating film, and particularly relates to a method of manufacturing a semiconductor single crystal layer using a beam annealing method. .

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

最近、電子ビームやレーザによるアニールで、絶縁膜上
にシリコン単結晶層を形成する、所謂Ｓｏｌ　（Ｓｉｌ
ｉｃｏｎ　　Ｏｎ　Ｉｎ５ｕｌａｔｏｒ）技術の開発が
盛んに行われている。また、このＳｏｌ技術を利用して
素子を３次元的に形成する、所謂３次元ＩＣの開発も進
められている。Recently, so-called Sol (Sil
(icon On In5lator) technology is being actively developed. Furthermore, the development of so-called three-dimensional ICs, in which elements are formed three-dimensionally using this Sol technology, is also underway.

電子ビームアニール或いはレーザピームアニールによっ
て絶縁膜上にシリコン単結晶層を作成する際には、第４
図に示す如く被アニール試料４１上で電子ビーム４２（
或いはレーザ）を走査し、半導体膜を帯溶融させる。そ
して、このビーム走査により、シリコン単結晶層の面積
を大きくしている。When creating a silicon single crystal layer on an insulating film by electron beam annealing or laser beam annealing, the fourth
As shown in the figure, an electron beam 42 (
or a laser) to melt the semiconductor film. By this beam scanning, the area of the silicon single crystal layer is increased.

しかしながら、この種の方法にあっては次のような間色
があった。即ち、前記第４図にも示す如く走査ビームの
重なりの部分が生じることになり、この部分で結晶が不
均一になる。また、走査開始点近傍及び終止点近隣で結
晶が不均一になる等の問題があった。However, this type of method has the following drawbacks. That is, as shown in FIG. 4, a portion where the scanning beams overlap occurs, and the crystal becomes non-uniform in this portion. Further, there was a problem that the crystal became non-uniform near the scanning start point and the end point.

〔発明の目的〕[Purpose of the invention]

本発明はこのような事情を考慮してなされたもので、そ
の目的とするところは、走査ビームの重なりに起因する
結晶の不均一性を抑制することができ、絶縁膜上に大面
積で良質の半導体単結晶層を成長形成し得る半導体単結
晶層の製造方法を提供することにある。The present invention was made in consideration of these circumstances, and its purpose is to suppress the non-uniformity of crystals caused by overlapping scanning beams, and to provide high-quality materials over a large area on an insulating film. An object of the present invention is to provide a method for manufacturing a semiconductor single crystal layer that can grow and form a semiconductor single crystal layer.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、エネルギービームを走査する代りに、
該ビームのスポット径を徐々に小さくすることにより、
半導体膜の溶融部分を溶融領域の周辺部から中心部へ向
かって固化させることにある。The gist of the invention is that instead of scanning an energy beam,
By gradually reducing the spot diameter of the beam,
The purpose is to solidify the molten portion of the semiconductor film from the periphery of the molten region toward the center.

即ち本発明は、絶縁膜上に多結晶若しくは非晶質の半導
体膜を形成したのち、該半導体膜上に保護膜を形成し、
次いでエネルギービームを用い上記半導体膜をアニール
して単結晶化する半導体単結晶層の製造方法において、
前記ビームアニールする際のビームの照射中心位置を固
定すると共に、該ビームのスポット径を半導体膜の単結
晶化すべき領域より大きくし、スポット径及びビーム強
度を徐々に小さくしていくようにした方法である。That is, the present invention forms a polycrystalline or amorphous semiconductor film on an insulating film, and then forms a protective film on the semiconductor film,
In a method for manufacturing a semiconductor single crystal layer, the semiconductor film is then annealed using an energy beam to become a single crystal.
A method of fixing the irradiation center position of the beam during the beam annealing, making the beam spot diameter larger than the area of the semiconductor film to be single-crystalized, and gradually decreasing the spot diameter and beam intensity. It is.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、所望のアニール領域を同時に溶融させ
ることが可能であり、走査ビームの重なり部分等の影響
を避けることができる。つまり、半導体膜の溶融部分を
その周辺から中央部へ向かって固化することにより、溶
融領域の再結晶化を連続して行うことができる。このた
め、単結晶化する半導体層の結晶均一性の大幅な向上を
はかり得る。According to the present invention, desired annealing regions can be melted at the same time, and the influence of overlapping portions of scanning beams can be avoided. That is, by solidifying the molten portion of the semiconductor film from the periphery toward the center, the molten region can be continuously recrystallized. Therefore, it is possible to significantly improve the crystal uniformity of the semiconductor layer to be made into a single crystal.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の゛詳細を図示の実施例によって説明する
。Hereinafter, details of the present invention will be explained by referring to illustrated embodiments.

第１図は本発明の一実施例方法に使用した電子ビームア
ニール装置を示す概略構成図である。図中１１は電子銃
であり、この電子銃１１から放射された電子ビーム１２
は静電レンズ１３及び対物レンズ１４を・介して被アニ
ール試料１５上に照射される。ここで、電子ビーム１２
のビーム径はレンズ１３．１４の励磁電流若しくは電圧
等を変化することにより可変されるものとなっている。FIG. 1 is a schematic diagram showing an electron beam annealing apparatus used in an embodiment of the present invention. 11 in the figure is an electron gun, and an electron beam 12 emitted from this electron gun 11
is irradiated onto the sample to be annealed 15 via the electrostatic lens 13 and the objective lens 14. Here, the electron beam 12
The beam diameter can be varied by changing the excitation current or voltage of the lenses 13 and 14.

さらに、ビーム強度も可変されるものとなっている。Furthermore, the beam intensity is also variable.

なお、図中１６は試料１５の単結晶化すべき領域、１７
は試料１６を保持する試料ホルダーを示している。In addition, 16 in the figure is a region to be single crystallized in sample 15, and 17
indicates a sample holder that holds the sample 16.

次に、上記装置を用いた半導体単結晶層の製造方法につ
いて説明する。第２図（ａ）〜（Ｃ）はシリコン単結晶
層製造工程を示す断面図である。Next, a method for manufacturing a semiconductor single crystal layer using the above apparatus will be described. FIGS. 2(a) to 2(C) are cross-sectional views showing the silicon single crystal layer manufacturing process.

まず、第２図（ａ）に示す如く面方位（１００）の単結
晶シリコン基板２１上に居間絶縁膜である厚さ０．２［
μｍ］のシリコン酸化膜２２を形成し、この酸化膜２２
を選択エツチングして幅２［μｍｌ、５００［μｍ口］
の開孔部（シード部）２３を形成する。なお、開孔部２
３にはテーバが付くようにする。次いで、第２図（ｂ）
に示す如く全面に厚さ０．６［μＴｒＬ］の多結晶シリ
コン膜（半導体膜）２４．厚さ０．３［μｍ］のシリコ
ン窒化膜２５及び厚さ０．１［μＴｒＬ］のタングステ
ン膜２６を順次形成する。ここで、上記シリコン窒化膜
２５及びタングステンＩＩ！１２６は多結晶シリコン１
１！２４をご一ムアニールする際の保護膜として作用す
るもので、これらの代りにシリコン酸化膜を用いること
も可能である。First, as shown in FIG. 2(a), a living room insulating film with a thickness of 0.2 [
μm] silicon oxide film 22 is formed, and this oxide film 22
Select and etch the width 2 [μml, 500 [μm]
An opening portion (seed portion) 23 is formed. Note that the opening 2
3 should have a tab. Next, Fig. 2(b)
As shown in the figure, a polycrystalline silicon film (semiconductor film) 24. with a thickness of 0.6 [μTrL] is formed on the entire surface. A silicon nitride film 25 with a thickness of 0.3 [μm] and a tungsten film 26 with a thickness of 0.1 [μTrL] are sequentially formed. Here, the silicon nitride film 25 and tungsten II! 126 is polycrystalline silicon 1
It acts as a protective film when the 1!24 is annealed, and a silicon oxide film can also be used in place of these.

次いで、前記第１図に示す装置を用い、まずスポット径
１［Ｍ］の電子ビームにより多結晶シリコンＩ！２４を
加熱溶融する。しかるのち、電子ビーム１２のスポット
径を徐々に小さくし、第２図（Ｃ）に示す如く周辺部か
ら中心部に向かう方向に溶融したシリコン１１！２４を
固化して単結晶化した。ここで、電子ビーム１２のスポ
ット径は第３図（ａ）〜（ｄ）に示す如く最初はシード
部２３より大きいものとし、アニール時間の経過と共に
徐々に小ざくなるようにした。また、スポット径の減小
と共にビーム強度も小さくし、ビーム照射部におけるビ
ーム電流密度は常に一定になるようにした。その結果、
シード部２３に囲まれた５００［μｍ口］の均一な単結
晶１ｌ１２４′が得られた。Next, using the apparatus shown in FIG. 1, polycrystalline silicon I! is first irradiated with an electron beam having a spot diameter of 1 [M]. 24 is heated and melted. Thereafter, the spot diameter of the electron beam 12 was gradually reduced, and the molten silicon 11!24 was solidified into a single crystal in the direction from the periphery to the center as shown in FIG. 2(C). Here, the spot diameter of the electron beam 12 was initially set to be larger than the seed portion 23 as shown in FIGS. 3(a) to 3(d), and was made to gradually become smaller as the annealing time progressed. In addition, as the spot diameter was reduced, the beam intensity was also reduced so that the beam current density at the beam irradiation part was always constant. the result,
A uniform single crystal 11124' with a diameter of 500 [μm] surrounded by the seed portion 23 was obtained.

かくして本実Ｍｊ、例方法によれば、多結晶シリコン膜
２４のアニールに際し、ビーム径及びビーム強度を徐々
に小さくしてことにより、走査ビームを用いた場合のよ
うなビーム重なりを生じることなく、多結晶シリコン膜
２４を単結晶化することができる。このため、大面積に
亙り均一なシリコン単結晶層２４′を得ることができる
。また、本実施例方法では、最初のビーム径の大きざを
定めることにより、単結晶化すべき領域を自由に設定す
ることができる。つまり、どのような大きさの領域であ
っても、電子ビームのビーム径の初期設定１直を可変す
るのみで容易に適用することができる等の利点がある。Thus, according to the present method, the beam diameter and beam intensity are gradually reduced during annealing of the polycrystalline silicon film 24, thereby avoiding beam overlap unlike when using a scanning beam. The polycrystalline silicon film 24 can be made into a single crystal. Therefore, a uniform silicon single crystal layer 24' can be obtained over a large area. Furthermore, in the method of this embodiment, by determining the size of the initial beam diameter, the region to be single-crystalized can be freely set. That is, there is an advantage that the present invention can be easily applied to any size region by simply changing the initial setting of the beam diameter of the electron beam.

なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記電子ビームの代りにはレーザど−
ムを用いることも可能である。また、単結晶化する半導
体膜は多結晶シリコンに限るものではなく、非晶質シリ
コンでもよく、さらにシリコンの代りにゲルマニウムや
ガリウムヒ素等を用いることも可能である。また、下地
絶縁膜及び保護膜の材料やその形成方法によって、本発
明の効果が減するものではないことは明らかである。さ
らに、前記島融点金属としてはタングステンの代りに、
チタン、モリブデン或いはこれらの合金を用いることも
可能である。また、それぞれの膜厚、シード部の大きざ
及び形状等も仕様に応じて適宜変更可能であるのは勿論
のことである。Note that the present invention is not limited to the method of the embodiment described above. For example, a laser can be used instead of the electron beam.
It is also possible to use a system. Further, the semiconductor film to be made into a single crystal is not limited to polycrystalline silicon, but may be amorphous silicon, and germanium, gallium arsenide, etc. can also be used instead of silicon. Further, it is clear that the effects of the present invention are not diminished depending on the materials of the base insulating film and the protective film and the method of forming them. Furthermore, instead of tungsten as the island melting point metal,
It is also possible to use titanium, molybdenum or alloys thereof. Further, it goes without saying that the thickness of each film, the size and shape of the seed portion, etc. can be changed as appropriate depending on the specifications.

その他、本発明の要旨を逸脱しない範囲で、種々変形し
て実施することができる。In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例方法に使用した電子ビームア
ニール装置を示す概略構成図、第２図（ａ）〜（Ｃ）は
本発明の一実施例方法に係わるシリコン単結晶層製造工
程を示す断面図、第３図（ａ）〜（ｄ）はビームスポッ
ト径の変化状態を示す模式図、第４図は従来方法の問題
点を説明するための模式図である。 １１・・・電子銃、１２・・・電子ビーム、１３・・・
静電レンズ、１４・・・対物レンズ、１５・・・被アニ
ール試料、１６・・・単結晶化すべき領域、２１・・・
単結晶シリコン基板、２２・・・シリコン酸化膜　（層
間絶縁Ｉり、２３・・・開孔部（シード部）、２４・・
・多結晶シリコン族（半導体８り、２４’　・・・シリ
コン単結晶層、２５・・・シリコン窒化膜、２６・・・
タングステンＩ！（高融点金属膜）。 出願人　工業技術院長　等々力　達 第　１ｖ！ＪFIG. 1 is a schematic configuration diagram showing an electron beam annealing apparatus used in an embodiment method of the present invention, and FIGS. 2(a) to (C) are silicon single crystal layer manufacturing steps according to an embodiment method of the present invention. FIGS. 3(a) to 3(d) are schematic diagrams showing changes in beam spot diameter, and FIG. 4 is a schematic diagram for explaining problems with the conventional method. 11...electron gun, 12...electron beam, 13...
Electrostatic lens, 14... Objective lens, 15... Sample to be annealed, 16... Area to be single crystallized, 21...
Single crystal silicon substrate, 22... silicon oxide film (interlayer insulation layer), 23... opening (seed part), 24...
・Polycrystalline silicon group (semiconductor 8, 24'...silicon single crystal layer, 25...silicon nitride film, 26...
Tungsten I! (High melting point metal film). Applicant: Director of the Agency of Industrial Science and Technology Tatsu Todoroki 1st v! J

Claims (4)

【特許請求の範囲】[Claims] （１）絶縁膜上に多結晶若しくは非晶質の半導体膜を形
成したのち、該半導体膜上に保護膜を形成し、次いでエ
ネルギービームを用い上記半導体膜をアニールして単結
晶化する半導体単結晶層の製造方法において、前記ビー
ムアニールする際のビームの照射中心位置を固定すると
共に、該ビームのスポット径を前記半導体膜の単結晶化
すべき領域より大きくし、スポット径及びビーム強度を
徐々に小さくしていくことを特徴とする半導体単結晶層
の製造方法。(1) After forming a polycrystalline or amorphous semiconductor film on an insulating film, a protective film is formed on the semiconductor film, and then an energy beam is used to anneal the semiconductor film to make it into a single crystal. In the method for manufacturing a crystal layer, the irradiation center position of the beam during the beam annealing is fixed, the spot diameter of the beam is made larger than the area to be made into a single crystal of the semiconductor film, and the spot diameter and beam intensity are gradually increased. A method for manufacturing a semiconductor single crystal layer, characterized by reducing the size of the semiconductor single crystal layer. （２）前記スポット径及びビーム強度の変化に拘りなく
、ビーム照射される部分のビーム電流密度を一定にした
ことを特徴とする特許請求の範囲第１項記載の半導体単
結晶層の製造方法。(2) The method for manufacturing a semiconductor single crystal layer according to claim 1, characterized in that the beam current density in a portion irradiated with the beam is kept constant regardless of changes in the spot diameter and beam intensity. （３）前記半導体膜はシリコンであり、前記保護膜はシ
リコン酸化膜またはシリコン窒化膜及び高融点金属膜を
順次形成したものであることを特徴とする特許請求の範
囲第１項記載の半導体単結晶層の製造方法。(3) The semiconductor film according to claim 1, wherein the semiconductor film is silicon, and the protective film is formed by sequentially forming a silicon oxide film or a silicon nitride film and a high melting point metal film. Method of manufacturing a crystal layer. （４）前記高融点金属は、タングステン、チタン、モリ
ブデン或いはこれらの合金であることを特徴とする特許
請求の範囲第３項記載の半導体単結晶層の製造方法。(4) The method for manufacturing a semiconductor single crystal layer according to claim 3, wherein the high melting point metal is tungsten, titanium, molybdenum, or an alloy thereof.
JP60040324A 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer Granted JPS61201415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60040324A JPS61201415A (en) 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60040324A JPS61201415A (en) 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer

Publications (2)

Publication Number Publication Date
JPS61201415A true JPS61201415A (en) 1986-09-06
JPH0236055B2 JPH0236055B2 (en) 1990-08-15

Family

ID=12577425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60040324A Granted JPS61201415A (en) 1985-03-02 1985-03-02 Manufacture of semiconductor single crystal layer

Country Status (1)

Country Link
JP (1) JPS61201415A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0216720A (en) * 1988-07-04 1990-01-19 Sanyo Electric Co Ltd Solid phase epitaxy method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119717A (en) * 1982-12-25 1984-07-11 Agency Of Ind Science & Technol Manufacture of single crystal semiconductor thin-film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119717A (en) * 1982-12-25 1984-07-11 Agency Of Ind Science & Technol Manufacture of single crystal semiconductor thin-film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0216720A (en) * 1988-07-04 1990-01-19 Sanyo Electric Co Ltd Solid phase epitaxy method

Also Published As

Publication number Publication date
JPH0236055B2 (en) 1990-08-15

Similar Documents

Publication Publication Date Title
US7029961B2 (en) Method for optimized laser annealing smoothing
US4589951A (en) Method for annealing by a high energy beam to form a single-crystal film
JP2002237455A (en) Silicon crystallization apparatus and method therefor
US6635555B2 (en) Method of controlling crystallographic orientation in laser-annealed polycrystalline silicon films
US6709910B1 (en) Method for reducing surface protrusions in the fabrication of lilac films
JPS6115319A (en) Manufacture of semiconductor device
JPS61201415A (en) Manufacture of semiconductor single crystal layer
JPS62160781A (en) Laser light projecting apparatus
JP2000111950A (en) Manufacture of polycrystalline silicon
JPH02112227A (en) Manufacture of semiconductor crystal layer
JP2714109B2 (en) Crystal film manufacturing method
JPS6347256B2 (en)
JPS6147627A (en) Manufacture of semiconductor device
JPH0136970B2 (en)
JP2740281B2 (en) Method for producing crystalline silicon
JPS59147425A (en) Formation of semiconductor crystal film
JPS6292427A (en) Semiconductor-manufacturing device
JPH0793261B2 (en) Single crystal thin film forming equipment
JPS58114435A (en) Laser annealiing method
JPS63224318A (en) Manufacture of substrate for semiconductor device
JPH0449250B2 (en)
JPS60191089A (en) Manufacture of single crystal thin film
JPS59119717A (en) Manufacture of single crystal semiconductor thin-film
JPS6092607A (en) Electron beam annealing device
JPH0775223B2 (en) Method for manufacturing semiconductor single crystal layer

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term