JPH02165996A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02165996A JPH02165996A JP63320442A JP32044288A JPH02165996A JP H02165996 A JPH02165996 A JP H02165996A JP 63320442 A JP63320442 A JP 63320442A JP 32044288 A JP32044288 A JP 32044288A JP H02165996 A JPH02165996 A JP H02165996A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chips
- semiconductor device
- sides
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 9
- 230000010354 integration Effects 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract description 8
- 230000001070 adhesive effect Effects 0.000 abstract description 8
- 239000011810 insulating material Substances 0.000 abstract description 3
- 238000001035 drying Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Landscapes
- Credit Cards Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は特にICメモリーチップを実装してなるメモリ
ーカードに好適な半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention particularly relates to a semiconductor device suitable for a memory card mounted with an IC memory chip.
(従来の技術)
最近、電子計算機等のデーターの外部記憶装置として、
メモリ用集積回路(以下メモリー用ICとする)を複数
個搭載した半導体装置が開発されている。(Prior art) Recently, as an external storage device for data of electronic computers, etc.
2. Description of the Related Art Semiconductor devices equipped with a plurality of memory integrated circuits (hereinafter referred to as memory ICs) have been developed.
この半導体装置へのメモリー用ICの実装方法としてプ
リント回路基板上にパッケージされたメモリー用ICを
配置し、このICのリード端子とプリント回路基板の配
線パターンをハンダ付けでするか、裸のメモリー用IC
チップ(以下ICチップとする)をプリント回路基板上
にマウントした後、このICチップのポンディングパッ
ドとプリント回路の配線パターンをワイヤーボンディン
グでつなぐ方法などが一般に用いられている。As a method of mounting a memory IC in this semiconductor device, a packaged memory IC is placed on a printed circuit board, and the lead terminals of this IC are soldered to the wiring pattern of the printed circuit board, or a bare memory IC is mounted on the printed circuit board. IC
A commonly used method is to mount a chip (hereinafter referred to as an IC chip) on a printed circuit board and then connect the bonding pads of the IC chip to the wiring pattern of the printed circuit by wire bonding.
ところで、別の実装方法として、第3図(a)、(b)
に示すように複数のICチップ11を相対的位置精度高
く配置するため、相対的位置を規定している半導体装置
のフレーム12の開口部13に、配線用電極端子がある
面を上側にしてそれぞれICチップ11を入れ接着剤1
4等で固定することで略同−平面状にし、この平面上に
スルホール用の開口部15を設けた感光性フィルム16
等による絶縁層を必要に応じて積層し、印刷配線17に
より電気回路を作成する方法が提案されている。By the way, as another mounting method, Fig. 3 (a) and (b)
In order to arrange a plurality of IC chips 11 with high relative positional accuracy as shown in FIG. Insert IC chip 11 and glue 1
A photosensitive film 16 that is fixed with 4 or the like to form a substantially coplanar shape and has an opening 15 for a through hole on this plane.
A method has been proposed in which insulating layers such as those described above are laminated as necessary and an electric circuit is created using printed wiring 17.
この実装方法はパッケージ化されたICではなく、裸の
ICチップを用いるため使用する部品のコストが低く、
位置決め精度の高いチップマウント装置やワイヤーボン
ディング装置も必要としない利点がある。This mounting method uses bare IC chips rather than packaged ICs, so the cost of the parts used is low;
It has the advantage of not requiring a chip mount device or wire bonding device with high positioning accuracy.
しかしこの方法を用いた場合、絶縁層を片側に形成する
ため、熱圧着による熱応力が片側にのみにかかり、半導
体装置に反りが生じやすく、これを防ぐために裏側にチ
ップ実装面積に相当する補強板を入れる等の対策が必要
となる。However, when this method is used, since the insulating layer is formed on one side, the thermal stress due to thermocompression bonding is applied only to one side, which tends to cause warping of the semiconductor device.To prevent this, the back side is reinforced with an area equivalent to the chip mounting area. Measures such as installing a board will be required.
(発明が解決しようとする課題)
従来方法による、半導体装置の絶縁層が片面のみである
ため、感光性フィルムを被着させるために熱圧着すると
、熱応力によってソリが生じるので、本発明は半導体装
置基板フレームの両面に感光性フィルムを両面同時に熱
圧着により被着させることにより、半導体装置の反りを
防ぐことを目的とする。(Problem to be Solved by the Invention) Since the insulating layer of a semiconductor device is only on one side by the conventional method, warping occurs due to thermal stress when thermocompression bonding is applied to attach a photosensitive film. The purpose of this method is to prevent warpage of semiconductor devices by simultaneously applying photosensitive films to both sides of a device substrate frame by thermocompression bonding.
(課題を解決するための手段)
本発明は複数個の集積回路(IC)チ・ノブを基板に略
同一平面上に配置して、このICチ・ノブの配線を施し
てなる半導体装置において、基板面に感光性フィルムを
被着させて形成した絶縁層にスルーホールを設けてから
印刷配線を施した半導体装置である。(Means for Solving the Problems) The present invention provides a semiconductor device in which a plurality of integrated circuit (IC) chips are arranged on a substrate substantially on the same plane, and the IC chips are wired. This is a semiconductor device in which through holes are provided in an insulating layer formed by applying a photosensitive film to a substrate surface, and then printed wiring is applied.
(作 用)
本発明の如く、基板フレームの両面に絶縁層を形成する
ことにより、半導体装置の反りを防ぐことが可能となる
。また、基板の裏面の絶縁層に表面と同様なスルホール
を形成させて配線することにより、両面からの配線引き
出しが可能となる。(Function) By forming insulating layers on both sides of the substrate frame as in the present invention, it is possible to prevent warping of the semiconductor device. Furthermore, by forming through holes similar to those on the front surface of the insulating layer on the back surface of the substrate and wiring them, it becomes possible to draw out the wires from both sides.
(実施例)
第1図は本発明の実施例である半導体装置の製造工程を
示す平面図および断面図である。(Example) FIG. 1 is a plan view and a cross-sectional view showing the manufacturing process of a semiconductor device according to an example of the present invention.
まず、第1図(a)〜(d)に示すように、ガラスエポ
キシ、又はセラミックス等の絶縁材料から成り、両面に
凹部50.51をもつ支持基体(以下、基板と称する)
1の両凹面に、導電性接着剤2を載せ、ICチップ(3
)を複数個挿入した後に基準とする一辺にICチップを
寄せながら、ICチ・ツブと基板との隙間に樹脂等の接
着剤4を入れ隙間を埋めて固定する。First, as shown in FIGS. 1(a) to (d), a supporting base (hereinafter referred to as a substrate) is made of an insulating material such as glass epoxy or ceramics and has recesses 50 and 51 on both sides.
A conductive adhesive 2 is placed on both concave surfaces of 1, and an IC chip (3
) After inserting a plurality of chips, an adhesive 4 such as a resin is put into the gap between the IC chip and the board, filling the gap and fixing the IC chip, while moving the IC chip to one side as a reference.
さらに、第1図(θ)、(f)に示すように、絶縁層と
して使用するための感光性フィルム5を両面にそれぞれ
熱圧着により、被着させこれに、ICチップ電極端子部
分と配線部分に接続させるためのスルホール6のパター
ン及び基板端子接続ノ々ターンが任意の位置に形成され
たメタルマスク等のフォトマスクを使用して、露光機等
の紫外線照射装置により両面の感光性フィルム5に露光
を行う。Furthermore, as shown in FIGS. 1(θ) and (f), a photosensitive film 5 to be used as an insulating layer is adhered to both sides by thermocompression bonding, and the IC chip electrode terminal portion and wiring portion are covered with the photosensitive film 5. Using a photomask such as a metal mask in which a pattern of through-holes 6 for connection to the board and board terminal connection no-turns are formed at arbitrary positions, the photosensitive film 5 on both sides is exposed using an ultraviolet irradiation device such as an exposure machine. Perform exposure.
つぎに、第1図(g) 、(h)に示すように、溶剤タ
イプの現像液を被露光面、全面にスプレー等により吹き
付ける方法で現像処理を行うことにより、スルホール6
を形成させたあと乾燥、硬化させて絶縁面を形成する。Next, as shown in FIGS. 1(g) and 1(h), the through holes 6 are developed by spraying a solvent type developer onto the exposed surface and the entire surface.
After forming, dry and harden to form an insulating surface.
つぎに、表面、裏面にそれぞれ、印刷によって配線7を
形成させて、ICチップの電極端子と基板電極端子との
接続を計り、併せて基板の両面から配線を引き出す。Next, wiring 7 is formed by printing on each of the front and back surfaces to connect the electrode terminals of the IC chip and the electrode terminals of the substrate, and the wiring is drawn out from both sides of the substrate.
第2図は本発明の他の実施例を示す平面図および断面図
である。FIG. 2 is a plan view and a sectional view showing another embodiment of the present invention.
まず、第2図(a) 、(b)に示すように、ガラスエ
ポキシ、又はセラミックス等の絶縁材料から成る開口部
60をもつ支持基体(以下、基板と称する)61の片面
に耐熱性のある粘着テープ62を開口を覆うように貼り
、更に開口部60に対応する形状の耐熱性の被粘着テー
プ83を貼る。このテープ63の表面には要所要所に導
電性接着剤64が載せである。First, as shown in FIGS. 2(a) and 2(b), a support base (hereinafter referred to as a substrate) 61 having an opening 60 made of an insulating material such as glass epoxy or ceramics is coated with a heat-resistant material on one side. An adhesive tape 62 is pasted to cover the opening, and a heat-resistant adhesive tape 83 having a shape corresponding to the opening 60 is further pasted. A conductive adhesive 64 is placed on the surface of this tape 63 at key points.
つぎに第2図(e) 、(d)に示すように、開口部を
上にして底面に載せた導電性接着剤64に対応する位置
にICチップ65複数個を挿入し基準とする一辺にIC
チップを寄せながら、ICチップ65と基板61の開口
部端面との隙間に樹脂等の接着剤66を入れ、隙間を埋
めてICチップ65を固定する。Next, as shown in FIGS. 2(e) and 2(d), a plurality of IC chips 65 are inserted into positions corresponding to the conductive adhesive 64 placed on the bottom surface with the opening facing up, and placed on one side as a reference. IC
While bringing the chips together, an adhesive 66 such as a resin is put into the gap between the IC chip 65 and the end surface of the opening of the substrate 61, filling the gap and fixing the IC chip 65.
さらに、第2図(e)に示すように、絶縁層として使用
するための感光性フィルム67を支持基体61の上面に
熱圧着により被着させたうえで、基板B1の裏面に貼っ
である耐熱性のテープ62を剥がし感光性フィルム68
を熱圧着により被着させ、これにICチップ電極端子部
分と配線部分に接続させるためのスルホールが形成され
たメタルマスク等のフォトマスクを使用して、露光機等
の紫外線照射装置により基板両面の感光性フィルムに露
光を行う。Furthermore, as shown in FIG. 2(e), a photosensitive film 67 to be used as an insulating layer is adhered to the upper surface of the supporting base 61 by thermocompression bonding, and a heat-resistant film 67 is attached to the back surface of the substrate B1. Peel off the photosensitive tape 62 and remove the photosensitive film 68.
Using a photomask such as a metal mask with through holes formed to connect to the IC chip electrode terminals and wiring parts, both sides of the board are coated by thermocompression bonding using an ultraviolet irradiation device such as an exposure machine. Expose the photosensitive film.
つぎに、第2図(f’) 、(g)に示すように、溶剤
タイプの現像液を被露光面の全面にスプレー等により吹
き付ける方法で現像処理を行うことにより、スルホール
69を形成、乾燥、硬化させて絶縁層面を形成する。つ
ぎに、第2図(h) 、(I)に示すように、基体61
の表面、裏面にそれぞれ、印刷により印刷配線70を形
成させることにより、基板両面からの配線を引き出した
。Next, as shown in FIGS. 2(f') and (g), through-holes 69 are formed and dried by performing a developing process by spraying a solvent type developer over the entire surface to be exposed. , and harden to form an insulating layer surface. Next, as shown in FIGS. 2(h) and (I), the base 61
By forming printed wiring 70 on the front and back sides of the substrate by printing, wiring was drawn out from both sides of the substrate.
[発明の効果]
半導体装置の両面に、絶縁層を形成させることにより反
りの防止がおこなわれ、両面からの配線の引き出しが可
能である。又実施例で示すように、半導体装置の両面に
、ICチップを実装することにより、ICチップの集積
度を従来より大幅にアップさせる。[Effects of the Invention] By forming insulating layers on both sides of the semiconductor device, warpage is prevented, and wiring can be drawn out from both sides. Furthermore, as shown in the embodiments, by mounting IC chips on both sides of a semiconductor device, the degree of integration of the IC chips can be greatly increased compared to the conventional method.
第1図は本発明の実施例を示す製造工程図、第2図は本
発明の他の実施例を示す製造工程図、第3図は従来装置
を説明する図である。
1・・・支持基体、
2・・・導電性接着剤、
3・・・ICチップ、
5・・・感光性フィルム、
6・・・スルーホール、
7・・・配線。
代理人 弁理士 則 近 憲 佑
同 松山光之
第1図
!
第2図FIG. 1 is a manufacturing process diagram showing an embodiment of the present invention, FIG. 2 is a manufacturing process diagram showing another embodiment of the invention, and FIG. 3 is a diagram explaining a conventional device. DESCRIPTION OF SYMBOLS 1... Support base, 2... Conductive adhesive, 3... IC chip, 5... Photosensitive film, 6... Through hole, 7... Wiring. Agent Patent Attorney Noriyuki Chika Yudo Mitsuyuki Matsuyama Figure 1! Figure 2
Claims (2)
配置して、前記集積回路チップの配線を施してなる半導
体装置において、前記基板の全面に感光性フィルムを被
着させて形成した絶縁層に、スルホールを設けてから印
刷配線を施したことを特徴とする半導体装置。(1) A semiconductor device in which a plurality of integrated circuit chips are arranged on a substrate substantially on the same plane and the integrated circuit chips are wired, and the semiconductor device is formed by covering the entire surface of the substrate with a photosensitive film. A semiconductor device characterized in that printed wiring is applied after providing through holes in an insulating layer.
積いっぱいに配置し、両面より、配線を引き出し、集積
回路チップの集積度を高めること、および集積回路チッ
プを両面に配置することを特徴とする請求項1記載の半
導体装置。(2) The printed wiring method is used to place the entire effective area on both sides of the board, and the wiring is drawn out from both sides to increase the degree of integration of the integrated circuit chip, and the integrated circuit chips are placed on both sides. The semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63320442A JPH02165996A (en) | 1988-12-21 | 1988-12-21 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63320442A JPH02165996A (en) | 1988-12-21 | 1988-12-21 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02165996A true JPH02165996A (en) | 1990-06-26 |
Family
ID=18121496
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63320442A Pending JPH02165996A (en) | 1988-12-21 | 1988-12-21 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02165996A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170139399A1 (en) * | 2014-03-05 | 2017-05-18 | Tokyo Electron Limited | Substrate processing apparatus, substrate processing method and memory medium |
-
1988
- 1988-12-21 JP JP63320442A patent/JPH02165996A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170139399A1 (en) * | 2014-03-05 | 2017-05-18 | Tokyo Electron Limited | Substrate processing apparatus, substrate processing method and memory medium |
US10528028B2 (en) * | 2014-03-05 | 2020-01-07 | Tokyo Electron Limited | Substrate processing apparatus, substrate processing method and memory medium |
US11287798B2 (en) | 2014-03-05 | 2022-03-29 | Tokyo Electron Limited | Substrate processing capable of suppressing a decrease in throughput while reducing the impact on exposure treatment caused by warping of a substrate |
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