JPH05226385A - Packaging of semiconductor device - Google Patents
Packaging of semiconductor deviceInfo
- Publication number
- JPH05226385A JPH05226385A JP2881292A JP2881292A JPH05226385A JP H05226385 A JPH05226385 A JP H05226385A JP 2881292 A JP2881292 A JP 2881292A JP 2881292 A JP2881292 A JP 2881292A JP H05226385 A JPH05226385 A JP H05226385A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor chip
- frame body
- board
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の実装方法
にかかり、半導体チップをダイパッドに搭載するに際
し、接着剤のはみ出しを防ぎ、クリーン化実装を行う方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device, and more particularly to a method for mounting a semiconductor chip on a die pad, preventing the adhesive from protruding, and performing a clean mounting.
【０００２】[0002]
【従来の技術】近年、混成集積回路の高密度実装におけ
る軽薄短小高機能化の傾向は高まる一方である。2. Description of the Related Art In recent years, there has been an increasing trend toward light, thin, short, small and high functionality in high density packaging of hybrid integrated circuits.
【０００３】従来、図８および図９に示すように、パッ
ケージングのなされていないベアＩＣチップ９（以下半
導体チップと指称する）とパッケージング後の個別電子
部品４とを同一基板１上に搭載する混成集積回路と呼ば
れるものが広く用いられている。Conventionally, as shown in FIGS. 8 and 9, a bare IC chip 9 not packaged (hereinafter referred to as a semiconductor chip) and an individual electronic component 4 after packaging are mounted on the same substrate 1. What is called a hybrid integrated circuit is widely used.
【０００４】このような混成集積回路において、半導体
チップ９の搭載は、半導体チップを搭載すべきダイパッ
ド６上に銀ペーストなどの接着剤８を塗布し、この上に
半導体チップをマウントすることによってなされる。し
かしながら、この場合接着剤のコントロールを厳しく管
理する必要があり、適量の接着剤が塗布されなければ接
着剤がダイパッド６の領域からはみだし、リード端子側
の電極パッド５に付着し短絡を生じたりするという問題
がある。In such a hybrid integrated circuit, the semiconductor chip 9 is mounted by applying an adhesive 8 such as silver paste on the die pad 6 on which the semiconductor chip is to be mounted and mounting the semiconductor chip thereon. It However, in this case, it is necessary to strictly control the control of the adhesive, and if an appropriate amount of adhesive is not applied, the adhesive will stick out from the area of the die pad 6 and adhere to the electrode pad 5 on the lead terminal side to cause a short circuit. There is a problem.
【０００５】このような問題を解決すべく、ダイパッド
６とリード端子側の電極パッド５との間を広くするとい
う方法も提案されているが、この方法では高密度化を阻
むことになる上、ワイヤボンディングに時間がかかると
いう問題があった。これは多ピン化が進むとさらに深刻
な問題となり、生産性の向上を阻む大きな理由の１つと
なっていた。In order to solve such a problem, there has been proposed a method of widening the space between the die pad 6 and the electrode pad 5 on the lead terminal side, but this method hinders high density, and There is a problem in that wire bonding takes time. This has become a more serious problem as the number of pins increases, and it has been one of the major reasons preventing improvement in productivity.
【０００６】[0006]
【発明が解決しようとする課題】このように、従来の実
装方法では、接着剤がダイパッドの領域からはみだし、
リード端子側の電極パッドに付着し短絡を生じたりする
という問題がある。As described above, in the conventional mounting method, the adhesive protrudes from the area of the die pad,
There is a problem that the electrode sticks to the lead terminal side to cause a short circuit.
【０００７】本発明は、前記実情に鑑みてなされたもの
で、接着剤のはみだしを防止し、信頼性の高い実装を行
うことのできる半導体装置の実装方法を提供することを
目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device mounting method capable of preventing the adhesive from squeezing out and mounting with high reliability.
【０００８】[0008]
【課題を解決するための手段】そこで本発明では、プリ
ント基板表面のダイパッド上あるいはその周囲に表面か
ら突出する枠体を形成するようにしている。この枠体は
耐熱性の樹脂または金メッキを施した導体パターン等で
構成され、位置決めマークの役割をもたせることも可能
である。Therefore, in the present invention, a frame body protruding from the surface is formed on or around the die pad on the surface of the printed circuit board. This frame is composed of a heat-resistant resin or a gold-plated conductor pattern or the like, and can also serve as a positioning mark.
【０００９】[0009]
【作用】上記方法によれば、接着剤はこの枠体の内部に
充填されるため、はみ出しはなく、半導体チップ搭載領
域に良好に半導体チップをボンディングすることができ
る。またこの枠体は半導体チップの位置決めの役割をも
有する。According to the above method, since the adhesive is filled inside the frame body, there is no protrusion and the semiconductor chip can be satisfactorily bonded to the semiconductor chip mounting region. The frame also has a role of positioning the semiconductor chip.
【００１０】[0010]
【実施例】次に、本発明の実施例について、図面を参照
しつつ詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１１】図１(a) および(b) は、本発明実施例の方
法で用いられるプリント基板１の斜視図および断面図、
図２はこのプリント基板の製造工程を示すフローチャー
トである。1 (a) and 1 (b) are a perspective view and a sectional view of a printed circuit board 1 used in a method of an embodiment of the present invention.
FIG. 2 is a flowchart showing the manufacturing process of this printed circuit board.
【００１２】図１(a) および(b) に示すように、このプ
リント基板１は、積層基板上に銅箔を貼着しこれをパタ
ーニングして配線パターン２およびダイパッド６を形成
しさらにこのダイパッド６上に厚膜印刷により厚さ２０
μm の金パターンからなる枠体を形成したことを特徴と
するものである。まず、銅張積層板と呼ばれる、熱硬化
性樹脂と紙およびガラス等の基材とを積層した積層板上
に銅箔を張り合わせたものを形成する（ステップ１０
０）。次に、スルーホールを形成する（ステップ１０
１）。As shown in FIGS. 1 (a) and 1 (b), the printed circuit board 1 has a laminated board on which a copper foil is adhered and patterned to form a wiring pattern 2 and a die pad 6, and further the die pad. 6 by thick film printing to a thickness of 20
It is characterized in that a frame made of a gold pattern of μm is formed. First, a copper clad laminate, which is formed by laminating a thermosetting resin and a base material such as paper and glass, on a copper foil is formed (step 10).
0). Next, a through hole is formed (step 10)
1).
【００１３】この後、マスクを形成して無電界銅めっき
法等により、スルーホール内に銅めっきを施し（ステッ
プ１０２）、さらにフォトリソグラフィにより配線パタ
ーンをエッチングしてパターン形成を行う（ステップ１
０３）この後ソルダレジストを印刷し（ステップ１０
４）、導体表面を表面処理する（ステップ１０５）。Thereafter, a mask is formed, copper is plated in the through holes by an electroless copper plating method or the like (step 102), and a wiring pattern is further etched by photolithography to form a pattern (step 1).
03) After this, solder resist is printed (step 10
4) The surface of the conductor is surface-treated (step 105).
【００１４】そして、さらに金の厚膜印刷によりコンポ
ーネントマークとしての枠体７を形成し（ステップ１０
６）、焼成を行い（ステップ１０７）本発明の方法で用
いられるプリント基板が完成する。次にこのプリント基
板を用いた混成集積回路装置の実装例について説明す
る。図３乃至図６はこの混成集積回路装置の実装工程を
示す図、図７はそのフローチャートである。実装に先立
ち部品を整備し（ステップ２０１）、プリント基板上の
固着位置にクリーム半田を印刷する（ステップ２０
２）。Then, a frame 7 as a component mark is formed by gold thick film printing (step 10).
6) Then, firing is performed (step 107) to complete the printed circuit board used in the method of the present invention. Next, a mounting example of a hybrid integrated circuit device using this printed board will be described. 3 to 6 are views showing a mounting process of this hybrid integrated circuit device, and FIG. 7 is a flowchart thereof. Prior to mounting, the parts are maintained (step 201), and cream solder is printed on the fixing position on the printed board (step 20).
2).
【００１５】そして、図３に示すように、図１(a) およ
び(b) に示したプリント基板１の配線パターン２上のク
リーム半田上に位置決めしてチップコンデンサ等の電子
部品４を搭載し（ステップ２０３）リフロー工程によっ
て半田を溶かし電子部品を固着する（ステップ２０
４）。ここで５はリード端子の電極パッドである。そし
て不要な半田ボールおよび汚れ等を洗浄によって除去す
る（ステップ２０５）。次いで図４に示すように、ダイ
パッド６上に銀ペースト８を塗布する。このとき、枠体
７の存在により銀ペーストのはみだしは防止される。Then, as shown in FIG. 3, an electronic component 4 such as a chip capacitor is mounted by positioning it on the cream solder on the wiring pattern 2 of the printed board 1 shown in FIGS. 1 (a) and 1 (b). (Step 203) The reflow process melts the solder to fix the electronic component (Step 20).
4). Here, 5 is an electrode pad of the lead terminal. Then, unnecessary solder balls, dirt and the like are removed by cleaning (step 205). Next, as shown in FIG. 4, the silver paste 8 is applied onto the die pad 6. At this time, the presence of the frame body 7 prevents the silver paste from protruding.
【００１６】そして図５に示すように半導体チップ９を
ダイパッド６上に搭載し（ステップ２０６）加熱固着す
る（ステップ２０７）。このとき枠体７の存在により位
置合わせ効果もあるため、高精度に位置決めを行うこと
ができる。この枠体の厚さは位置合わせ効果と接着剤は
み出し防止効果を十分に得るには数十μm 以上とするの
が望ましい。Then, as shown in FIG. 5, the semiconductor chip 9 is mounted on the die pad 6 (step 206) and fixed by heating (step 207). At this time, since the presence of the frame body 7 also has a positioning effect, it is possible to perform positioning with high accuracy. It is desirable that the thickness of the frame body be several tens of μm or more in order to sufficiently obtain the alignment effect and the adhesive protrusion prevention effect.
【００１７】この後図６に示すように半導体チップ９の
ボンディングパッド１０とプリント基板１上の電極パッ
ド５との間をボンディングワイヤ１１を介して接続し
（ステップ２０８）、ボンディング状態を検査したのち
（ステップ２０９）、樹脂１２によって封止を行う（ス
テップ２１０）。そして硬化炉で硬化を行い（ステップ
２１１）、最終検査（ステップ２１２）を経て、ハイブ
リッドＩＣが完成する（ステップ２１３）。なお、前記
実施例においては、枠体を厚膜印刷で形成した金膜で構
成したが、金めっき層を用いてもよくまた耐熱性の樹脂
で構成しても良い。Thereafter, as shown in FIG. 6, the bonding pad 10 of the semiconductor chip 9 and the electrode pad 5 on the printed board 1 are connected via the bonding wire 11 (step 208), and the bonding state is inspected. (Step 209), the resin 12 is used for sealing (Step 210). Then, curing is performed in the curing furnace (step 211), and after a final inspection (step 212), the hybrid IC is completed (step 213). Although the frame is made of a gold film formed by thick film printing in the above embodiment, a gold plating layer may be used or a heat resistant resin may be used.
【００１８】また、プリント基板として積層基板を用い
たが、ガラス基板やセラミック基板、樹脂基板等を用い
てもよく、さらに配線パターンについても銅箔に限定さ
れることなく適宜変更可能である。Further, although the laminated board is used as the printed board, a glass board, a ceramic board, a resin board or the like may be used, and the wiring pattern is not limited to the copper foil and may be appropriately changed.
【００１９】さらに前記実施例では、チップと配線パタ
ーンとの間の接続はワイヤボンディングによって行うよ
うにしたが、必ずしもワイヤボンディングを用いる必要
はなく、フェイスダウン方式等のダイレクトボンディン
グを用いる際にも適用可能である。Furthermore, in the above-mentioned embodiment, the connection between the chip and the wiring pattern is made by wire bonding, but it is not always necessary to use wire bonding, and it is also applicable when face-down type direct bonding or the like is used. It is possible.
【００２０】[0020]
【発明の効果】以上説明したように、本発明では、プリ
ント基板の半導体素子搭載領域に枠体を形成し、接着剤
をこの枠体の内部に充填するようにしているため、接着
剤のはみ出しがなく良好に半導体チップ搭載領域に、半
導体チップをボンディングすることができる。As described above, according to the present invention, the frame is formed in the semiconductor element mounting region of the printed circuit board, and the adhesive is filled inside the frame. It is possible to satisfactorily bond the semiconductor chip to the semiconductor chip mounting area.
【図１】本発明実施例の方法で用いられるプリント基板
を示す図FIG. 1 is a diagram showing a printed circuit board used in a method according to an embodiment of the present invention.
【図２】同プリント基板の形成工程図。FIG. 2 is a process drawing of the same printed circuit board.
【図３】本発明実施例の方法を用いたハイブリットＩＣ
の実装工程を示す工程図。FIG. 3 is a hybrid IC using the method of the embodiment of the present invention.
FIG.
【図４】本発明実施例の方法を用いたハイブリットＩＣ
の実装工程を示す工程図。FIG. 4 is a hybrid IC using the method of the embodiment of the present invention.
FIG.
【図５】本発明実施例の方法を用いたハイブリットＩＣ
の実装工程を示す工程図。FIG. 5: Hybrid IC using the method of the embodiment of the present invention
FIG.
【図６】本発明実施例の方法を用いたハイブリットＩＣ
の実装工程を示す工程図。FIG. 6 is a hybrid IC using the method of the embodiment of the present invention.
FIG.
【図７】本発明実施例の実装工程を示すフローチャート
図。FIG. 7 is a flowchart showing a mounting process of the embodiment of the present invention.
【図８】従来例の実装工程を示す工程図。FIG. 8 is a process diagram showing a mounting process of a conventional example.
【図９】従来例の実装工程を示す工程図。FIG. 9 is a process diagram showing a mounting process of a conventional example.
１ プリント基板 ２ 配線パターン ３ クリーム半田 ４ チップ部品 ５ 電極パッド ６ ダイパッド ７ 枠体 ８ 接着剤 ９ 半導体チップ １０ ボンディングパッド １１ ボンディングワイヤ １２ 樹脂 1 Printed Circuit Board 2 Wiring Pattern 3 Cream Solder 4 Chip Component 5 Electrode Pad 6 Die Pad 7 Frame 8 Adhesive 9 Semiconductor Chip 10 Bonding Pad 11 Bonding Wire 12 Resin
Claims (1)
半導体チップ実装領域のパターンに突起状の枠体を形成
する枠体形成工程と、 前記枠体内部に接着剤を充填し前記パターン上に半導体
チップを装着し接続するチップ搭載工程と、 前記配線パターンと半導体チップとを接続するボンディ
ング工程とを含むことを特徴とする半導体装置の実装方
法。1. A frame forming step of forming a protruding frame on a pattern of a semiconductor chip mounting region of a wiring pattern on a surface of a printed circuit board, and an adhesive is filled inside the frame to form a semiconductor chip on the pattern. A method of mounting a semiconductor device, comprising: a chip mounting step of mounting and connecting a semiconductor chip; and a bonding step of connecting the wiring pattern and a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2881292A JPH05226385A (en) | 1992-02-17 | 1992-02-17 | Packaging of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2881292A JPH05226385A (en) | 1992-02-17 | 1992-02-17 | Packaging of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05226385A true JPH05226385A (en) | 1993-09-03 |
Family
ID=12258826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2881292A Pending JPH05226385A (en) | 1992-02-17 | 1992-02-17 | Packaging of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05226385A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299553A (en) * | 1999-04-13 | 2000-10-24 | Ricoh Microelectronics Co Ltd | Manufacture of electronic circuit board |
| JP2008205057A (en) * | 2007-02-19 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2008218932A (en) * | 2007-03-08 | 2008-09-18 | Matsushita Electric Ind Co Ltd | Semiconductor element mounting substrate and its manufacturing method |
-
1992
- 1992-02-17 JP JP2881292A patent/JPH05226385A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299553A (en) * | 1999-04-13 | 2000-10-24 | Ricoh Microelectronics Co Ltd | Manufacture of electronic circuit board |
| JP2008205057A (en) * | 2007-02-19 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2008218932A (en) * | 2007-03-08 | 2008-09-18 | Matsushita Electric Ind Co Ltd | Semiconductor element mounting substrate and its manufacturing method |
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