JPH02165631A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH02165631A JPH02165631A JP32245988A JP32245988A JPH02165631A JP H02165631 A JPH02165631 A JP H02165631A JP 32245988 A JP32245988 A JP 32245988A JP 32245988 A JP32245988 A JP 32245988A JP H02165631 A JPH02165631 A JP H02165631A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- interlayer film
- oxide film
- layer wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に２層配線の交差部
における第２層配線の平担性が高い半導体集積回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which second-layer wiring has high flatness at the intersection of two-layer wiring.
従来、この種の２層配線の交差部はＳｉ基板上にＬＯＧ
Ｏ８酸化膜を成長させ層間膜、第１配線層間膜、第２配
線と積み重なった構造となっていた。Conventionally, the intersection of this type of two-layer wiring was formed using a LOG on a Si substrate.
An O8 oxide film was grown to form a stacked structure including an interlayer film, a first interconnect interlayer film, and a second interconnect.
上述した従来の２層配線の交差部は、平坦なＬＯＧＯ８
酸化膜上の層間膜の上に第１層配線を引く為１層配線と
２層配線の交差部ではこの第１層配線の段差がそのまま
第２層配線の段差につながり平担性を悪くするという欠
点がある。The intersection of the conventional two-layer wiring described above is a flat LOGO8
Since the first layer wiring is drawn on the interlayer film on the oxide film, at the intersection of the first layer wiring and the second layer wiring, the step difference in the first layer wiring directly leads to the step difference in the second layer wiring, worsening the flatness. There is a drawback.
本発明の半導体集積回路は２層配線の交差部の第１配線
の下のＬＯＣＯ８酸化膜を無くし、Ｓｉ基板上に層間膜
、第１配線２層間膜第２配線と積み重ねた構造を有して
いる。The semiconductor integrated circuit of the present invention eliminates the LOCO8 oxide film under the first wiring at the intersection of two-layer wiring, and has a structure in which an interlayer film, a first wiring, two interlayer films, and a second wiring are stacked on a Si substrate. There is.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図であり、Ｓｔ基板・
・・１．ＬＯＣＯ８酸化膜・・・２１層間膜（１）・・
・３、第１ Ａ Ｉ！・４ 、層間膜（２）−５、塗布
膜ａ、第２ＡＡにより構成される。FIG. 1 is a cross-sectional view of one embodiment of the present invention, in which the St substrate and
・・１． LOCO8 oxide film...21 interlayer film (1)...
・3.1st AI! -4, composed of interlayer film (2)-5, coating film a, and second AA.
第１Ａｌｌと第２ＡＡの交差部において交差面積よりや
や大きめにＬＯＧＯ３酸化膜を無くし、その凹の段差を
利用して第１ＡＩ２の段差を吸収する事により層間膜（
２）を付けた段階では表面はかなり平担化される。The interlayer film (
At the stage where 2) is applied, the surface is considerably flattened.
第３図は本発明の実施例２の断面図であり、Ｓｉ基板・
・・１．ＬＯＧＯ８酸化膜・・・２２層間膜・・・３゜
第１ＡＪ・・・４１層間膜・・・５．塗布膜・・・６．
第２ＡＩｌにより構成される。FIG. 3 is a cross-sectional view of Example 2 of the present invention, in which the Si substrate
・・１． LOGO8 Oxide film...22 Interlayer film...3° 1st AJ...41 Interlayer film...5. Coating film...6.
It is constituted by the second AIl.
この実施例では実施例１に対して交差部の第１Ａｌｌの
下の層間膜（１）をエツチングし、凹部なつくる事によ
り第１ＡＡの段差を吸収し、層間膜（２）を付けた段階
で表面を平担化できる。また実施例１のＬＯＣＯ８酸化
膜に対し工程が終りに近い層間膜（１）を使用する為修
正などが行いやすいという利点がある。In this example, in contrast to Example 1, the interlayer film (1) under the first All at the intersection is etched, a recess is created to absorb the step difference in the first A, and at the stage where the interlayer film (2) is attached. The surface can be flattened. Further, since the interlayer film (1) whose process is near the end is used compared to the LOCO8 oxide film of Example 1, there is an advantage that corrections can be easily made.
以上説明した様に本発明は第１配線と第２配線の交差部
における第１配線の下のＬＯＧＯ３酸化膜を無くす事に
より第１配線後の平担性が良くできるという効果がある
。As explained above, the present invention has the effect of improving the flatness after the first wiring by eliminating the LOGO3 oxide film under the first wiring at the intersection of the first wiring and the second wiring.
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図は従来のＩ
ＡＡと２ＡＡ’の交差部の断面図、第３図は本発明の第
２の実施例の断面図である。
１・・・・・・Ｓｉ基板、２・・・・・・ＬＯＣＯ８酸
化膜、３・・・・・・層間膜（１）、４・・・・・・第
１Ａｉ７．５・・・・・・層間膜（２）、６・・・・・
・塗布膜、７・・・・・・第２Ａ４゜代理人 弁理士
内 原 晋
図
第 ３１！Ｉ
手
閃[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a sectional view of one embodiment of the present invention, and Fig. 2 is a sectional view of a conventional I.
A sectional view of the intersection of AA and 2AA', and FIG. 3 is a sectional view of a second embodiment of the present invention. 1... Si substrate, 2... LOCO8 oxide film, 3... Interlayer film (1), 4... First Ai7.5...・Interlayer film (2), 6...
・Coating film, 7...2nd A4゜Representative patent attorney
Susumu Uchihara drawing No. 31! I hand flash
Claims (1)
前記交差部の第１層配線の下の層間膜厚を減らすかもし
くは無くす事を特徴とする半導体集積回路。At the intersection of the first layer wiring and the second layer wiring of the two-layer wiring,
A semiconductor integrated circuit characterized in that the interlayer film thickness under the first layer wiring at the intersection is reduced or eliminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32245988A JPH02165631A (en) | 1988-12-20 | 1988-12-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32245988A JPH02165631A (en) | 1988-12-20 | 1988-12-20 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02165631A true JPH02165631A (en) | 1990-06-26 |
Family
ID=18143891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32245988A Pending JPH02165631A (en) | 1988-12-20 | 1988-12-20 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02165631A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071283A (en) * | 2007-08-07 | 2009-04-02 | Rohm Co Ltd | Semiconductor device |
-
1988
- 1988-12-20 JP JP32245988A patent/JPH02165631A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071283A (en) * | 2007-08-07 | 2009-04-02 | Rohm Co Ltd | Semiconductor device |
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