JPH0334429A - Wiring structure of semiconductor device - Google Patents
Wiring structure of semiconductor deviceInfo
- Publication number
- JPH0334429A JPH0334429A JP16884689A JP16884689A JPH0334429A JP H0334429 A JPH0334429 A JP H0334429A JP 16884689 A JP16884689 A JP 16884689A JP 16884689 A JP16884689 A JP 16884689A JP H0334429 A JPH0334429 A JP H0334429A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- width
- film
- trench
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000000630 rising effect Effects 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000012528 membrane Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001698 pyrogenic effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は半導体装置の配線構造に関し、より詳しくは同
じ配線幅を実現するのに、従来の必要な面積より小さな
面積で済む半導体装置の配線構造に関する。Detailed Description of the Invention [Industrial Application Field 1] The present invention relates to a wiring structure for a semiconductor device, and more specifically, a wiring structure for a semiconductor device that requires a smaller area than the conventional one to realize the same wiring width. Regarding structure.
［従来の技術］
従来、半導体装置の配線は、平坦な基板上に第３図に示
すように、幅がＬの配線は基板上でＬだけの幅のスペー
スを必要としていた。特に電源ライン（ｖＣＣ９ＧＮＤ
）は配線幅が広く、ＩＣチップの面積の縮小化の妨げに
なっていた。[Prior Art] Conventionally, as shown in FIG. 3, wiring for a semiconductor device has a width L on a flat substrate and requires a space of width L on the substrate. Especially the power line (vCC9GND
) had a wide wiring width, which was an obstacle to reducing the area of the IC chip.
一方、■配線の段差性と段差形状についての報告がある
（Ｈｏｍｍａ、Ｙ、、Ｔｕｎｅｋａｗａ、Ｓ、、 ”
ＰｌａｎａｒＤｅｐｏｓｉｔｉｏｎ ｏｆ Ａｌｕｍｉ
ｎｕｍ ｂｙ ＲＦ／ＤＣＳｐｕｔｔｅｒｉｎｇｗｉｔ
ｈ ＲＦ Ｂｉａｓ、 ” Ｊ、Ｅｌｅｃｔｒｏｃｈｅ
ｍ、 Ｓｏｃ、、Ｖｏｌ、１３２Ｎｏ、６．ｐｐ 、１
４６６〜１４７２．（１９８５）；Ｂｌｅｃｋ、１．Ａ
、。On the other hand, there are reports on the level difference characteristics and shape of wiring (Homma, Y., Tunekawa, S., 2003).
PlanarDeposition of Aluminum
num by RF/DC Sputteringwit
h RF Bias, ” J, Electroche
m, Soc,, Vol, 132 No., 6. pp, 1
466-1472. (1985); Bleck, 1. A
,.
“Ｅｖａｐｏｒａｔｉｏｎ Ｆｉｌｍ Ｐｒｏｆｉｌｅ
ｓ ０ｖｅｒ ５ｔｅｐｓ １ｎＳｕｂｓｔｒａｔｅｓ
、 ” Ｔｈ１ｎ ５ｏｌｉｄ Ｆｉｌｍｓ、Ｖｏｌ、
６．ｐｐ、１１３〜１１８． （１９７０）参照）
また、■配線パターンの下地となる材料の加工に関する
報告がある（川水ほか、「サブミクロン・ドライプロセ
ス」、「昭和５７年電気四学会連合大会講演論文集３Ｊ
、ｐ、３〜５． （１９８２）参照〉。“Evaporation Film Profile
s 0ver 5teps 1nSubstrates
,” Th1n 5olid Films, Vol.
6. pp, 113-118. (1970)) There are also reports on the processing of materials that serve as the base for wiring patterns (Kawamizu et al., ``Submicron Dry Process'', ``Proceedings of the 1981 Electrical Engineers of Japan Federation Conference 3J
, p. 3-5. (1982)>.
［発明が解決しようとする課題］
ところが、上記■の報告は半導体装置の配線において、
たまたま生じる段差部におけるメタルの被覆シミューレ
ーションに関するもので、また、上記■は、段差を傾斜
をつけてエツチングする技術であり、配線の大部分は、
第３図のように、幅Ｌの配線は基板上でＬだけのスペー
スを必要としていた。[Problem to be solved by the invention] However, the above report (■) shows that in the wiring of semiconductor devices,
This is related to the simulation of metal coating on a step that happens to occur, and the above method (■) is a technique for etching the step at an angle, and most of the wiring is
As shown in FIG. 3, a wiring having a width L requires a space of L on the board.
本発明は上記の点を解決しようとするもので、その目的
は、配線幅りを確保しながらも、基板上での必要とする
面積は第３図に示された場合の面積より小さくできる半
導体装置の配線構造を提供することにある。The present invention is an attempt to solve the above-mentioned problems, and its purpose is to create a semiconductor device that requires less area on the substrate than the area shown in FIG. 3 while ensuring the wiring width. The purpose of the present invention is to provide a wiring structure for the device.
［課題を解決するための手段］
本発明によれば、半導体基板上に溝を形成し、該溝上に
順次絶縁層、配線層を設けてなり、かつ、配線層は該溝
の少なくとも底部と立上り部を覆う幅を有することを特
徴とする半導体装置の配線構造が提供されるものである
。[Means for Solving the Problems] According to the present invention, a groove is formed on a semiconductor substrate, and an insulating layer and a wiring layer are sequentially provided on the groove, and the wiring layer is formed at least at the bottom of the groove and at the rising edge. There is provided a wiring structure for a semiconductor device characterized by having a width that covers the entire width of the semiconductor device.
〔作用］
基板に溝を設けその部分に配線領域を設けるために、溝
の深さの分だけ線幅を小さくして配線層を設けることが
できるようになる。[Operation] Since a groove is provided in the substrate and a wiring region is provided in the groove, a wiring layer can be provided with the line width reduced by the depth of the groove.
［実施例］ 次に実施例を挙げて本発明を説明する。[Example] Next, the present invention will be explained with reference to Examples.
第１図に本発明にかかる半導体装置の配線構造を示す。FIG. 1 shows the wiring structure of a semiconductor device according to the present invention.
第１図において、１は基板、２は溝、３は絶縁層、４は
配線層である。本実施例においては、配線層４は、溝２
と底部２ａと立上り部２ｂと縁部２Ｃとにまたがって形
成されている。すなわち、基板に溝２を設けその部分に
配線領域を設け、溝の深さの分だけ配線を小さくできる
。従って、基板上で同じ配線幅を実現するのに従来必要
であった面積より小さな面積で済ますことができるよう
になる。In FIG. 1, 1 is a substrate, 2 is a groove, 3 is an insulating layer, and 4 is a wiring layer. In this embodiment, the wiring layer 4 has the groove 2
It is formed astride the bottom portion 2a, the rising portion 2b, and the edge portion 2C. That is, by providing a trench 2 in the substrate and providing a wiring region in that portion, the wiring can be made smaller by the depth of the trench. Therefore, the area required to realize the same wiring width on the board can be smaller than that required in the past.
次に本発明の配線構造を形成するプロセスについて説明
する。Next, a process for forming the wiring structure of the present invention will be explained.
まず、Ｓｉ基板１ａ上にＳｉ３Ｎ４膜（窒化膜〉５を形
成する［第２図（ａ）参照］。First, a Si3N4 film (nitride film) 5 is formed on the Si substrate 1a [see FIG. 2(a)].
次に、フォトリソグラフィーの技術により８１３Ｎ４膜
５を選択的にエツチングする［第２図（ｂ）参照］この
エツチングのパターンは配線のパターンに相当する。Next, the 813N4 film 5 is selectively etched by photolithography (see FIG. 2(b)). This etching pattern corresponds to a wiring pattern.
次に、酸化（スチームあるいはパイロジェニック）によ
り酸化膜（Ｓ！Ｏｚ＞６を形成する［第２図（Ｃ）参照
コ。（この酸化は第２図（Ｃ＞における深さＤが〜５ｏ
ｏｏ７Ｓ％になるまで行う。）次いで、Ｓ ｉ ０２膜
６及び５ｉ３Ｎ４５のエツチングを行う（深さ〜５００
０Ａになるまで行う。）［第２図（ｄ）参照］。Next, an oxide film (S!Oz>6 is formed by oxidation (steam or pyrogenic) [see Figure 2 (C)).
Continue until it reaches oo7S%. ) Next, the Si02 film 6 and 5i3N45 are etched (depth ~500 mm).
Continue until it reaches 0A. ) [see Figure 2(d)].
ＰＳＧまたはＢＰＳＧよりなる絶縁層３を形成（厚ざ〜
２５０〇八）後、Ａ１等による配線層４（厚ざ〜６００
０Ａ ＞を形成する［第２図（ｅ）参照］。Form an insulating layer 3 made of PSG or BPSG (with a thickness of
25008), then wiring layer 4 (thickness ~ 600mm) using A1 etc.
0A> [see FIG. 2(e)].
次に、フォトリソグラフィーの技術により配線領域を形
成する。この配線領域は上記で形成した溝２の少なくと
も底部２ａと立上り部２ｂを覆う幅とする［第２図（ｆ
）参照１゜第２図（ｆ）においては縁部２Ｃまで覆うよ
うに配線領域が形成されている。Next, a wiring region is formed using photolithography technology. This wiring area has a width that covers at least the bottom part 2a and the rising part 2b of the groove 2 formed above [Fig.
) Reference 1° In FIG. 2(f), the wiring area is formed so as to cover up to the edge 2C.
第２図（ｆ＞のように形成された配線層は、従来しだけ
必要であった配線が１ （＜Ｌ）で済むようになり、
配線の面積を従来より小ざくすることができ、ＩＣチッ
プの面積の縮小が可能となった。The wiring layer formed as shown in Fig. 2 (f>) requires only one wiring (<L), which was previously required
The area of the wiring can be made smaller than before, making it possible to reduce the area of the IC chip.
［発明の効果］
以上の説明で明らかなように本発明の配線構造により、
基板上での配線に要する面積を従来より小ざくすること
ができ、ＩＣチップの面積の縮小化（寄与することがで
きる。[Effects of the Invention] As is clear from the above explanation, the wiring structure of the present invention provides
The area required for wiring on the substrate can be made smaller than before, which can contribute to the reduction of the area of the IC chip.
第１図は本発明に係る半導体装置の配線構造を示す断面
説明図、第２図（ａ）〜第２図（ｆ＞は本発明の配線構
造を形成する際のプロセスの例を示す断面説明図、第３
図は従来の半導体装置の配線構造を示す断面説明図であ
る。
１・・・基板、１ａ・・・３ｉ基板、２・・・溝、２ａ
・・・底部、２ｂ・・・立上り部、２Ｃ・・・縁部、３
・・・絶縁層、４・・・配線層、
５・・・Ｓｉ３Ｎ４膜（窒化ＩＩＩ）、６・・・ＳｉＯ
２膜（ｉ１！化膜）。FIG. 1 is a cross-sectional explanatory diagram showing the wiring structure of a semiconductor device according to the present invention, and FIGS. Figure, 3rd
The figure is an explanatory cross-sectional view showing the wiring structure of a conventional semiconductor device. 1...Substrate, 1a...3i substrate, 2...Groove, 2a
...bottom, 2b...rising part, 2C...edge, 3
...Insulating layer, 4...Wiring layer, 5...Si3N4 film (III nitride), 6...SiO
2 membrane (i1! conversion membrane).
Claims (1)
層を設けてなり、かつ、配線層は該溝の少なくとも底部
と立上り部を覆う幅を有することを特徴とする半導体装
置の配線構造。Wiring for a semiconductor device, characterized in that a groove is formed on a semiconductor substrate, and an insulating layer and a wiring layer are sequentially provided on the groove, and the wiring layer has a width that covers at least the bottom and rising parts of the groove. structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16884689A JPH0334429A (en) | 1989-06-30 | 1989-06-30 | Wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16884689A JPH0334429A (en) | 1989-06-30 | 1989-06-30 | Wiring structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0334429A true JPH0334429A (en) | 1991-02-14 |
Family
ID=15875623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16884689A Pending JPH0334429A (en) | 1989-06-30 | 1989-06-30 | Wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0334429A (en) |
-
1989
- 1989-06-30 JP JP16884689A patent/JPH0334429A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01290236A (en) | Method of levelling wide trench | |
| JPH0334429A (en) | Wiring structure of semiconductor device | |
| JPH11121457A (en) | Manufacture of semiconductor device | |
| JPS5992547A (en) | Isolation process | |
| JPS61119056A (en) | Manufacture of semiconductor device | |
| JP3079530B2 (en) | Semiconductor device | |
| JPH08107112A (en) | Method of forming interconnection semiconductor device | |
| KR100253586B1 (en) | Method of forming cell aperture mask of semiconductor device | |
| JPH0497523A (en) | Manufacture of semiconductor device | |
| KR100312983B1 (en) | A method for forming isolation layer in semiconductor device | |
| JP3087702B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20070002594A (en) | Method for forming overlay vernier of semiconductor device | |
| JPS62262441A (en) | Manufacture of semiconductor device | |
| JPH0737873A (en) | Method of forming element separation region of semiconductor device | |
| JPS63271957A (en) | Formation of multilayer interconnection | |
| JPH03257925A (en) | Forming method of wiring pattern | |
| JPS6386451A (en) | Semiconductor device | |
| JPS59105339A (en) | Manufacture of semiconductor device | |
| JPH01136349A (en) | Formation of inter-element isolation film of semiconductor device | |
| JPS6377164A (en) | Field-effect transistor | |
| JPS63122152A (en) | Semiconductor integrated circuit device | |
| JPS6336546A (en) | Wiring structure of semiconductor device and manufacture thereof | |
| JPS62200746A (en) | Semiconductor device | |
| KR970013196A (en) | Device isolation insulating film formation method of semiconductor device | |
| JPS6242435A (en) | Formation of electrode |