JPH02150059A - Semiconductor device using resistance element - Google Patents

Abstract

PURPOSE:To avoid a phenomenon in which the resistance value of a resistance element is varied in a reflowing step and to prevent the variation in the resistance values by forming an oxidation-resistance film on the substrate of a resistance element region. CONSTITUTION:An element insulating silicon oxide film 5 and a gate oxide film 8 are formed on a substrate 1. Thereafter, after a silicon nitride film of an oxidation-resistant film is grown, only a silicon film 6 of a region to be formed with a resistance element remains. Then, a gate polysilicon electrode 7 and a P-type diffused layer 2 are formed. A photoresist 11 is selectively formed on a region in which P-type high concentration impurity of the layer 3, etc. of a resistance region is not implanted. Subsequently, with the photoresist 11 and the electrode 7 as masks boron is implanted to the surface of the substrate to form P<+>-type diffused layers 2, 4. Then, after a BPSG film 9 is grown on the whole surface, it is steam-treated at 800 - 900 deg.C to reflow.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resistance element formed by a diffusion layer and an MIS
(Metal 1nsulator ser++1co
Regarding semiconductor devices in which bipolar transistors and 0MO3) type transistors coexist, especially bipolar transistors and
The present invention relates to a semiconductor device having a resistance element suitable for a BiCMO3 semiconductor device combined with a transistor.

[Conventional technology] In recent years, BiC, which achieves both low power consumption and high-speed operation, has become popular.
MO3 semiconductor devices are attracting attention. This BiCMO8
In a semiconductor device, in order to set the potential level of a bipolar transistor, a resistor element with a highly accurate resistance value is essential. For this reason, a diffusion layer formed on the surface of a semiconductor substrate is usually used as a resistance element.

FIG. 6 is a sectional view showing an example of a semiconductor device having a conventional resistance element. In FIG. 6, the silicon oxide film 25 formed on the surface of the N-type silicon substrate 21 causes
Region A, which is a resistance element formation region, and region B, which is a P channel MOS transistor formation region, are insulated and separated.

In the resistance element region A, a P+ type diffusion layer 22 is formed on the surface of an N type silicon substrate 21 at a predetermined distance. A P type diffusion layer 23 is formed between the P + type diffusion layers 22 and has both ends connected to the P + type diffusion layer 22 . This P-type diffusion 123 becomes a resistance element.

A gate oxide film 28 and a silicon oxide (hereinafter referred to as BPSG) film 29 doped with boron and phosphorus at a high concentration are formed on the surface of the silicon substrate 21. Membrane type 9BPSG membrane 2
A contact hole reaching the P+ type diffusion layer 22 from the nine-film type 9 is opened. Then, an aluminum silicon electrode 30 is formed filling this contact hole.

On the other hand, a gate oxide film 28 is formed on the silicon substrate 21 of the P-channel MO3) transistor region B, and a gate polysilicon electrode 27 is selectively formed on this gate oxide film 28.

Then, on the surface of the silicon substrate 21, a P+ layer is formed in self-alignment with the gate polysilicon electrode 27.
A type diffusion layer 24 is provided.

A BPSG film 29 is formed on the gate polysilicon electrode 27 and the gate oxide film 28.
A hole is provided that reaches the gate polysilicon electrode 27 from the surface of the nine-film type 9.

In addition, the BPSG film 29 film type 9-T oxide film 28 has BP
Contact holes are provided that reach the P+ type diffusion layer 24 from the film shape 9 of the SG film 29, and aluminum silicon electrodes 3o are formed by filling these holes.

The semiconductor substrate 21 includes the above-mentioned resistance element and P channel M.
In addition to the OS transistor, an N-channel transistor (O3) transistor, a bipolar transistor, etc. (not shown) are formed, but their explanation will be omitted.

In a BiCMO3 semiconductor device having a conventional resistance element, as described above, a diffusion layer resistance region (P-type diffusion layer 23) of a conductivity type opposite to that of the substrate 21 is formed on the surface of the semiconductor substrate 21 directly under the gate oxide film 28. is formed, and this diffusion layer is used as a resistance element.Also, the gate oxide film 2
An insulating film is formed on 2 using BPSG or PSG. This BPSG film or PSG film is reflowed in an oxidizing atmosphere in order to prevent problems such as disconnection from occurring in a later wiring process.

[Problems to be Solved by the Invention] However, in the process of reflowing this insulating film, the oxidizing atmosphere reaches the P-type diffusion layer 23 below the gate oxide film 28, oxidizing the surface layer of the P-type diffusion layer 23. There are things to do. Therefore, in a semiconductor device having a conventional resistance element, there is a drawback that the impurity elements in the P-type diffusion layer 23 are segregated, and the layer resistance changes greatly. and,
Since the rate at which the layer resistance changes varies depending on the thickness of the insulating film such as BPSG or PSG, the variation in resistance value on the same semiconductor substrate and between semiconductor devices is extremely large. For this reason, the potential level of the transistor connected to this resistance element deviates from the optimum value, resulting in problems such as a delay in response speed and deterioration of transistor characteristics.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor device having a resistance element that can always obtain good transistor characteristics by avoiding changes in resistance value due to an oxidizing atmosphere.

[Means for Solving the Problems] A semiconductor device having a resistance element according to the present invention is a semiconductor device in which a resistance element consisting of an MIS type transistor and a diffusion layer is formed on a semiconductor substrate. The semiconductor device is characterized by having an oxidation-resistant film formed on a semiconductor substrate excluding a region where the MIS type transistor is formed.

[Operation] In the present invention, an oxidation-resistant film is formed on the semiconductor substrate in the resistance element region, but this oxidation-resistant film is not formed in the MIS type transistor region. This results in
During reflow, the oxidizing atmosphere is blocked by this oxidation-resistant film and does not reach the surface of the diffusion layer in the resistance element region. Therefore, phenomena such as oxidation of the layer surface of the resistive element region and segregation of impurity elements are avoided, so that the resistance value of the diffusion layer hardly changes.

However, the oxidation-resistant film has the property of easily changing the characteristics of the MIS transistor.

Therefore, an oxidation-resistant film is not provided on the semiconductor substrate in the MIS transistor region, but an oxidation-resistant film is formed only on the semiconductor substrate in the resistance element region.

As a result, both the bipolar transistor and the MIS type transistor can obtain good transistor characteristics.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. In this figure, region A of semiconductor substrate 1 is a resistor element forming region, and region B is a P channel MOS transistor forming region.

This embodiment differs from the conventional semiconductor device having a resistor element described above in that the structure of the portion including the resistor element formed in region A is different, and the structure of the portion including the resistor element formed in region B is different.
Since the structures of the channel MoS transistors are substantially the same, only the resistance element in region A will be described.

This resistive element forming region A is insulated and isolated from other regions by a silicon oxide film 5 formed on an N-type silicon substrate 1. P+ type diffusion layers 2 are formed on the surface of the substrate 1 at a predetermined distance apart, and between the P+ type diffusion layers 2, a P type diffusion layer 3 has both ends connected to the P+ type diffusion layers 2. It is formed by connecting with. A gate oxide film 8 is formed on the substrate 1.
A silicon nitride rTA 6 is selectively formed on the gate oxide film 8 and the silicon oxide film 5 for insulation isolation. Then, BP, which is an insulating film, is applied to the entire surface.
An SG film 9 is formed. A contact hole reaching the P+ type diffusion layer 2 from the surface of the BPSG film 9 is formed in the BPSGWA 9, silicon nitride film 6, and gate oxide film 8, and an aluminum silicon electrode 10 is formed by filling this contact hole. It is formed.

FIGS. 2 and 3 are cross-sectional views showing the method of manufacturing a semiconductor device having a resistance element according to this embodiment in order of steps.

First, as shown in FIG. 2, a silicon oxide film 5 and a gate oxide film 8 for device insulation are formed on an N-type silicon substrate 1. After that, a silicon nitride film, which is an oxidation-resistant film, is applied.
After growing the silicon nitride film to a thickness of 0.00 mm, photolithography is used to form a silicon nitride film 6 in the area where the resistor element is to be formed.
The silicon nitride film in other regions is removed, leaving only the silicon nitride film remaining.

Next, as shown in FIG. 3, a gate polysilicon electrode 7 and a P-type diffusion layer 3 are formed by a predetermined method. Then, a photoresist 1°1 is applied to regions where P-type high concentration impurities are not introduced, such as the P-type diffusion layer 3 which is a resistance region, the emitter part of a bipolar transistor (not shown), and the N-channel MOS transistor (not shown). Form selectively. Thereafter, using the photoresist 11 and the gate polysilicon electrode 7 as a mask, boron is introduced into the substrate surface by ion implantation as shown by the arrow in the figure to create a P+ type diffusion layer as shown in FIG. Form 2 and 4.

Next, after growing a BPSG film 9 on the entire surface, this is
Reflow is performed by steam treatment at a temperature of 00 to 900°C. Thereafter, a P+
A hole reaching the type diffusion layers 2, 4 or the gate polysilicon electrode 7 is opened, and the hole is filled to form an aluminum silicon electrode 10. As a result, a semiconductor device having a resistance element is completed.

In this embodiment, since the silicon nitride film 6 is formed above the P-type diffusion layer 3 which becomes a resistance element, the BPSG
When performing steam treatment after growing the film 9, the silicon nitride film 6 can prevent an oxidizing atmosphere from entering the P-type diffusion N3. Therefore, oxidation of the P-type diffusion layer 3 and segregation of impurity elements are avoided, and a resistance element having a desired resistance value can be obtained.

In fact, when we manufactured a semiconductor device having a resistance element with a resistance value of 2 Ω at the center of the standard, the resistance value, which conventionally fluctuated within a range of ±30% with respect to the center of the standard, was changed to ±30% in this example. The variation was suppressed to within 15%.

Next, the reason why the silicon nitride film 6 is not formed in the MOS transistor formation region B will be explained. That is, in this embodiment, the silicon nitride film in the MOS transistor formation region B is removed by the process shown in FIG.

In the drain portion of the MOS transistor, the depletion layer spreads over a wide range because it is reverse biased during operation. In this depletion layer, accelerated carriers collide with the crystal lattice, so that charges are extremely likely to be generated. On the other hand, once a silicon nitride film captures charge, it is difficult to release the charge. For this reason, a charge exists in the silicon nitride film near the drain, and the MOS is affected by this charge.
Transistor characteristics change. To avoid this, the silicon nitride film in the MoS transistor region is removed.

Next, a second embodiment of the present invention will be described with reference to the cross-sectional view of FIG. 4.9 In this FIG. It is separated into a region A, a P channel M, and a region B which is an OS transistor formation region.

In region A, a gate oxide film 8 is formed on the silicon substrate 1.
is formed, and a silicon nitride film 16 is selectively formed on this gate oxide film 8. On the surface of the silicon substrate 1, P-type diffusion layers 13 and silicon nitride films 16, which are resistance elements, are formed in a self-aligned manner.
A + type diffusion N12 is formed. This P+ type diffusion layer 1
2 is compared to the P+ type diffusion layer 2 in the first embodiment,
It is formed shallowly.

BPSG is formed on the silicon nitride film 16 and the gate oxide film 8.
A film 9 is formed. A contact hole is provided in the BPSGM 9 and the gate oxide film 8, reaching the P' type scattering layer 12 from the surface of the BPSG [9, and an aluminum silicon electrode 10 is formed by filling this contact hole.

On the other hand, in region B, a gate oxide film 8 is formed on the substrate 1, and a gate polysilicon electrode 7 is selectively formed on this gate oxide film 8. A shallow P+ type diffusion layer 14 is formed on the surface of the substrate 1 in a self-aligned manner with respect to the gate polysilicon electrode 7.

B on the gate polysilicon electrode 7 and the gate oxide film S
A PSG film 9 is formed. A hole is provided in this BPSG film 9 and gate oxide film 8 to reach the gate polysilicon electrode 7 or P+ type diffusion 114 from the surface of the BPSG film 9, and an aluminum silicon electrode 10 is formed by filling this hole. It is formed.

Next, a method for manufacturing a semiconductor device having a resistance element according to this embodiment will be described.

FIG. 5 is a sectional view showing one step of the manufacturing method of this embodiment. First, as in the first embodiment, an N-type silicon substrate 1 is
An insulating oxide film 5, a gate oxide film 8, and a polysilicon gate electrode 7 are formed thereon, and a P-type impurity is introduced into the substrate surface to form a P-type diffusion layer 13. Thereafter, a silicon nitride film 16 is grown on the entire surface to a thickness of 2000 nm. and,
Using photolithography technology, only the silicon nitride film 16 above the P-type diffusion layer 13, which will become a resistance element, remains, and the silicon nitride film in other regions is removed.

Next, as indicated by arrows in the figure, boron is introduced into the silicon substrate 1 by ion implantation of BF2. As a result, as shown in FIG. 4, a P+ type diffusion layer 12.1.4 with a shallow junction depth is formed. Further, since the silicon nitride film 16 serves as a mask, high concentration impurities are not introduced into the type diffusion 113.

Thereafter, in the same manner as in the first embodiment, after growing the BPSG film 9, holes are formed in the BPSG film 9 and the gate oxide film 8, and the respective holes are filled to form an aluminum silicon electrode 10. do. As a result, a semiconductor device having the resistance element of this example is completed.

In the first embodiment, a P+ type diffusion layer 2 is formed to make ohmic contact with an aluminum silicon electrode 10. This P+ type diffusion layer 2 is formed simultaneously with the P+ type diffusion layer 4 of the P channel transistor. For this purpose, boron is introduced into the surface of the substrate 1 by accelerating the boron so as to pass through the silicon nitride pA 6 and the gate oxide film 8 by ion implantation.

However, the P+ type diffusion layer 4, which is the source and drain of the MOS transistor, is sometimes formed with a shallow junction depth in order to increase the speed of the device. In such a case, since the silicon nitride film 6 is formed in the resistance element region, the film thickness becomes thick, and boron is not sufficiently introduced into the surface of the substrate 1, and the P+ type diffusion layer 2 with a predetermined impurity concentration is not formed. can't get it. For this reason, aluminum silicon electrode 1
Ohmic contact with 0 cannot be formed.

However, in this embodiment, since the silicon nitride film 16 does not exist above the P+ type diffusion layer 12 in the resistance element region, even if the junction of the P+ type diffusion Ji 14 of the MoS transistor is formed shallowly, the P+ type diffusion layer 12 A P+ type diffusion layer 12 having the same impurity concentration as layer 14 can be obtained. This makes it possible to obtain a semiconductor device having a desired resistance value and an ohmic contact even in a high-speed semiconductor device.

[Effects of the Invention] As explained above, in the present invention, since an oxidation-resistant film is formed on the substrate in the resistance element region, it is possible to avoid a phenomenon in which the resistance value of the resistance element changes during the reflow process. Can be done. This prevents variations in resistance value and allows a resistive element having a desired resistance value to be stably obtained.

Therefore, the present invention has the effect that the characteristics of a bipolar transistor or the like can always be set to a desired value.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the first embodiment of the present invention, FIGS. 2 and 3 are sectional views showing the manufacturing method in the order of steps,
FIG. 4 is a sectional view showing a second embodiment of the present invention, FIG. 5 is a sectional view showing a manufacturing method thereof, and FIG. 6 is a sectional view showing an example of a semiconductor device having a conventional resistance element. . 1.21; N-type silicon substrate, 2, 4, 12° 14.2
2,24. P+ type diffusion layer, 3, 13, 23; P type diffusion layer, 5, 25; silicon oxide film, 6° 16; silicon nitride film, 7, 27: gate polysilicon electrode, 8.28; gate oxide film, 9 , 29, BPSG film, 10.30; Aluminum silicon electrode diagram

Claims (1)

[Claims] (1) In a semiconductor device in which a resistor element consisting of an MIS transistor and a diffusion layer is formed on a semiconductor substrate,
1. A semiconductor device having a resistance element, comprising an oxidation-resistant film formed on a semiconductor substrate including a region above the diffusion layer and excluding a region where the MIS type transistor is formed.