JPH02149184A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To attain gain lock quickly and accurately by quickening locking of a horizontal synchronizing signal while interleaving the horizontal synchronizing signal by intention, and locking the horizontal synchronizing signal and the vertical synchronizing signal. CONSTITUTION:The phase of a horizontal synchronizing signal H21 of a video signal generated by a video signal generating circuit based on an external synchronizing signal and a horizontal synchronizing signal H11 of a reference composite synchronizing signal are compared by a phase comparator circuit 29. When the phase difference exceeds 1H, the horizontal synchronizing signal H11 or H21 in the reference composite synchronizing signal or the synchronizing signal of the video signal is interleaved. Thus, the voltage level fed to a VCO 31 is changed and a signal in an oscillated frequency in response to the voltage level is outputted and used as an external synchronizing signal, then the period of the synchronizing signal of the video signal is changed based thereupon and the synchronizing signal of the video signal is locked to the phase of the reference composite synchronizing signal. Thus, the gain lock is implemented quickly and accurately.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked loop circuit, particularly a genlock (genlock).
The present invention relates to a phase-locked loop circuit suitable for Genlock) circuits.

[Summary of the invention]

The present invention provides a phase lock loop circuit that matches the phase of a synchronization signal of a video signal generated based on an external synchronization signal with the phase of a reference composite synchronization signal. A phase comparison circuit that compares the phase of the horizontal synchronization signal of the composite synchronization signal, a Vco that outputs a signal with a frequency corresponding to the output signal of the phase comparison circuit, a phase of the vertical synchronization signal of the video signal, and a reference composite synchronization circuit. Compare the phases of the vertical synchronization signals of the signals, and when the phase difference exceeds 1H,
A circuit for thinning out one horizontal synchronization signal of the reference composite synchronization signal input to the phase comparison circuit or the synchronization signal of the video signal generated by the video signal generation circuit, and by using the output of the VCO as an external synchronization signal. , it is possible to speed up the locking of the horizontal synchronization signal, and to perform genlock quickly and accurately.

[Conventional technology]

For example, when superimposing a computer graphics image onto an image played on a VTR, the synchronization signals of both video signals are matched, so-called genlock.
(ienlock) is required.

Conventional techniques for performing this genlock include the following.

■ Compare the vertical synchronization signals, oscillate the VCO with an error voltage according to the phase difference to form a dot clock (hereinafter referred to as a clock), and count this clock to generate the horizontal synchronization signal and vertical synchronization signal. Form.

(2) Comparing the horizontal synchronization signals, oscillating the VCO with an error voltage corresponding to the phase difference to form a clock, and counting this clock to form a horizontal synchronization signal and a vertical synchronization signal.

■Compares both horizontal and vertical synchronization signals,
The phase of the horizontal synchronization signal is compared, and the vertical synchronization signal is detected and a counter is operated to determine the interval between the vertical synchronization signals. In this way, the vertical synchronization signal and the horizontal synchronization signal are respectively synchronized, and then a clock is formed.

[Question H that the invention attempts to solve] The above-mentioned conventional technology has the following problems.

In case (2), since the interval between the vertical synchronization signals is long, there are few opportunities for error detection, and the stability of the oscillation frequency of the VCO is accordingly lacking. Also, it must have a large counter.

■ must be equipped with a large counter.

■The timing cannot be determined until the vertical synchronization signal and horizontal synchronization signal are synchronized to form a clock.
During this time, the DRAM and image processing circuits, such as scan converters, A/D converters, and D/A converters, must be stopped.

Therefore, an object of the present invention is to provide a phase-locked loop circuit that can quickly and accurately perform genlock.

[Means to solve the problem]

The present invention provides a phase lock loop circuit that matches the phase of a video signal synchronization signal generated by a video signal generation circuit based on an external synchronization signal with the phase of a reference composite synchronization signal. a phase comparison circuit that compares the phase of the horizontal synchronization signal of the reference composite synchronization signal with the phase of the horizontal synchronization signal of the reference composite synchronization signal; a VCO that outputs a signal with a frequency corresponding to the output signal of the phase comparison circuit; ,
The phases of the vertical synchronization signal of the reference composite synchronization signal are compared, and when the phase difference exceeds 1H, the reference composite synchronization signal input to the phase comparison circuit or the synchronization signal of the video signal generated by the video signal generation circuit is A circuit for thinning out one of the horizontal synchronizing signals is provided, and the output of the VCO is used as an external synchronizing signal.

[Effect]

A phase comparison circuit compares the phase of a horizontal synchronization signal of a video signal generated by a video signal generation circuit based on an external synchronization signal and a horizontal synchronization signal of a reference composite synchronization signal. If the phase difference exceeds 1H, one horizontal synchronization signal of the reference composite synchronization signal or the video signal synchronization signal is thinned out.

As a result, the level of the voltage supplied to the VCO changes, and a signal with an oscillation frequency corresponding to the level of the voltage is output. Since the oscillation output of the VCO is used as an external synchronization signal,
Based on this external synchronization signal, the period of the synchronization signal of the video signal changes. Eventually, the synchronization signal of the video signal is locked to the phase of the reference composite synchronization signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. This embodiment uses Genlock for a superimposer that adds a computer graphics video signal to a reproduced composite video signal.
k) The present invention is applicable to the circuit.

Terminal 1 shown in FIG. 1 is supplied with an external video signal SVI. This external video signal SVI is supplied to the ROB decoder 2 and the synchronization signal separation circuit 3, respectively.

The external video signal SVI is converted into R, G by RGB decoder 2.
, B into three primary color signals. Each primary color signal is supplied to a high frequency compression circuit 4 and subjected to high frequency compression. This high-frequency compression allows input signals that are higher than the reference signal to be displayed brightly on the monitor without causing whiteout. This primary color signal is then supplied to the A/D converter 5 and is converted into 18-bit (R, G.

B is a digital signal of 6 bits each. This digital signal is supplied to the scan converter 6, and the horizontal scanning frequency is set to 15.75 KH by a line memory, for example.
z is converted to 31.5KH2. The signal is then supplied to the switching circuit 7.

On the other hand, 8-bit graphics data output from the graphics data generation circuit 8 is supplied to a color palette 9, and 1-bit control data output from the graphics data generation circuit 8 is supplied to a key signal generator 10. Ru. The graphics data is converted from 8 bits to 18 bits by the color palette 9 and supplied to the switching circuit 7. Further, the control data is converted into a control signal for controlling the switching circuit 7 by the key signal generator 10. This control signal is transmitted to the switching circuit 7
and controls the switching circuit 7.

A switching circuit 7 switches between the digital signal supplied from the scan converter 6 mentioned above and the graphics data supplied from the color palette 9. Thereafter, the 18-bit digital signal or 18-bit graphics data is supplied to the D/A converter 11, converted into an analog video signal, and supplied to the monitor 12.

The external video signal SVt is supplied to the synchronization signal separation circuit 3, and the vertical synchronization signal 1 and the horizontal synchronization signal H1 are separated.
The signals are respectively supplied to the control circuit 13. Further, a vertical synchronizing signal (2) and a horizontal synchronizing signal H2 are also generated from the above-mentioned graphics data generating circuit 8 by dividing the clock CLK, and are supplied to the control circuit 13.

As shown in FIG. 2, the above-mentioned horizontal synchronizing signal H1 is sent to a field discrimination circuit 21, a first mask pulse generation circuit 22, a second mask pulse generation circuit 23,
Furthermore, it is supplied to the OR gate 24.

The vertical synchronizing signal (1) is supplied to the field discrimination circuit 21 and the vertical phase comparison circuit 26 via the terminal 25. On the other hand, the horizontal synchronizing signal H2 is passed through the terminal 26 to the 172 frequency divider circuit 27.
The vertical synchronizing signal V2 is supplied to the vertical phase comparison circuit 26 via the terminal 28.

The vertical synchronizing signal v1 and the horizontal synchronizing signal H1 are supplied to a field determining circuit 21, which determines whether the field is an odd field or an even field. The output signal from this field discrimination circuit 21 is supplied to a vertical phase comparison circuit 26 to control this vertical phase comparison circuit 26.

The vertical synchronization signals v1 and v2 are phase-compared in a vertical phase comparison circuit 26. If there is a phase difference of 18 or more, the output signal SΔV is transmitted to the first mask pulse generation circuit 22,
It is supplied to the second mask pulse generation circuit 23.

The horizontal synchronizing signal H2 shown in FIG. 3A is frequency-divided by 172 to form the horizontal synchronizing signal H20 shown in FIG. 3B. This horizontal synchronizing signal H20 is supplied to the first mask pulse generation circuit 22, the second mask pulse generation circuit 23, and further to the OR gate 28.

The output signal SΔV activates the first and second mask pulse generation circuits 22.23, respectively, and the first and second mask pulse generation circuits 22.23 generate horizontal synchronization signals H1, H
Mask pulse PMISPM2 is formed based on 2O. Mask pulse PMI, PH2 is OR gate 24.2
8 is output.

Mask pulse PM from first mask pulse generation circuit 22
I and the horizontal synchronization signal H1 are logically summed by an OR gate 24 to form a horizontal synchronization signal 111. This horizontal synchronization signal H1l is supplied to the horizontal phase comparison circuit 29.

Mask pulse PM from second mask pulse generation circuit 23
2 and the horizontal synchronizing signal H20 are logically summed by an OR gate 28 to produce a horizontal synchronizing signal H21. This horizontal synchronization signal H21 is supplied to the horizontal phase comparison circuit 29.

Horizontal synchronization signal H1l from OR gate 24.28,)1
21 are phase-compared at the falling edge in the horizontal phase comparator circuit 29 as shown in FIGS. 3B and 3C,
An error voltage Verl is formed according to the phase difference, and is supplied to the VCO 31 via the low-pass filter 30.

The concept of phase comparison and phase lock described above is shown in FIG. That is, if there is a phase difference between the horizontal synchronizing signal H21 shown in FIG. 4A and the horizontal synchronizing signal H21 shown in FIG. 4B, the dotted line shown in FIG. When the arrow part is removed, as shown in FIGS. 4C and 4, the period T of the horizontal synchronizing signal H21 is extended, the error voltage Ver1 becomes low level, the input voltage Ver2 of the VCO 31 decreases, and the VCO 31's The oscillation frequency also decreases. Gradually, the horizontal synchronization signal) 121, Hll
Since the phase difference of VCO 31 is reduced, the input terminal Ve of VCO 31
As r2 increases, the oscillation frequency of the VCO 31 also increases.

As a result, horizontal synchronization signals H1, H2, vertical synchronization signal ■1
, ■2 phase lock is achieved.

In this way, by masking one of the horizontal synchronizing signal devices 1 and H21 and intentionally omitting it, the horizontal synchronizing signal H1,
H2, the phase lock of the vertical synchronization signal VLV2 can be accelerated, and genlock can be performed quickly and accurately. and,
Since the phase locking of the horizontal synchronizing signals H1 and H2 and the vertical synchronizing signals H1 and V2 can be accelerated, the oscillation frequency of the VCO 31 can be stabilized. Furthermore, there is no need to have a large counter as in the past, and DRAM,
There is no need to stop the scan converter, A/D converter, D/A converter, etc.

The oscillation output signal changes to VC031 according to the input voltage Ver2.
It is formed as a clock CL. This clock CLK is returned to the graphics data generation circuit 8 via the terminal 32.

The control circuit 13 supplies the monitor 12 with a vertical synchronization signal H2 and a horizontal synchronization signal v2. The above-mentioned analog video signal is controlled by a vertical synchronizing signal H2 and a horizontal synchronizing signal 2, and is displayed on the monitor 12.

Incidentally, the external video signal SVI from the VTR has a vertical frequency of 60 Hz and a horizontal frequency of 31.5 KHz, while the graphics data from the graphics data generation circuit 8 has a vertical frequency of 70 Hz and a horizontal frequency of 31.5 KHz. It is 5KHz. Therefore, by adding the computer graphics raster to the top and bottom of the screen of the monitor 12, the vertical frequency of the graphics data is increased to 60.
) 1z, horizontal frequency is 31.5K) 1z. This conversion of vertical and horizontal frequencies facilitates superimposition. Note that this conversion increases the number of rasters, so with a simple parameter change, for example, a circle becomes a horizontally elongated ellipse. Therefore, the clock frequency of the graphics data generation circuit 8 is corrected by increasing it by the amount of the horizontal length (approximately 10%).

There are three types of phase relationships between the vertical synchronization signals 1 and v2 as follows.

(A) When vertical synchronization signals v1 and v2 are in the same phase Figure 5A
And FIG. 5C shows horizontal synchronization signals H1 and H2.

As shown in FIGS. 5B and 5, when the vertical synchronizing signal VL V2 is in phase, there is no output signal SΔν as a vertical phase error, as shown in FIG.
As shown in FIGS. 5F and 5G, the mask pulses PMI and PM2 are not output. Therefore, the falling edges of the horizontal synchronizing signals H1l and H21 shown in FIGS. 5H and 5I are masked. First, as shown in FIGS. 5J and 5K, neither the error voltage er1 nor the input voltage Ver2 is output.

In this state, the oscillation frequency from the VCO 31 is set to the free run frequency. Incidentally, the dotted line portions shown in FIGS. 5B and 5 indicate the output states of vertical synchronizing signals (1) and (2) in odd-numbered fields.

(B) When the vertical synchronization signal ■1 is ahead of the vertical synchronization signal ■2 by 18 or more As shown in Figure 6B and Figure 6, the vertical synchronization signal ■2 is ahead of the vertical synchronization signal ■2. If (1) is ahead by 18 or more, the output signal SΔV is kept at a high level from the fall of the vertical synchronization signal (1) to the fall of the vertical synchronization signal (2) as shown in FIG. As a result, at the timing shown in FIG. 6F, the mask pulse PM! only is considered to be at a high level. When the horizontal synchronizing signal H1 and the mask pulse PMI shown in FIG. 6F are logically summed, the falling edge of the horizontal synchronizing signal H1l is masked as shown in FIG. 6H,
The horizontal synchronization signal H1l continues to be at a high level.

In this case, as shown in FIGS. 6J and 6K, the error voltage V
Since erl becomes low level, the oscillation frequency from VC031 decreases, and the period T of the horizontal synchronization signal H21 increases. Hereinafter, following the process shown in FIG. 4, horizontal synchronizing signals H1, H2, vertical synchronizing signals ■1, ■
2 will be locked. Note that the dotted line portions shown in FIGS. 6B and 6 indicate the output states of the vertical synchronizing signals V1 and V2 in the case of odd fields.

(C) When the vertical synchronizing signal v1 is delayed by 1H or more with respect to the vertical synchronizing signal v2 As shown in FIG. 7B and FIG. If there is a delay of 1H or more, the output signal SΔV is kept at a high level from the fall of the vertical synchronization signal 2 to the fall of the vertical synchronization signal Vl, as shown in FIG. As a result, only the mask pulse PM2 is set to high level at the timing shown in FIG. 7G. When the horizontal synchronizing signal H20 and the mask pulse PM2 shown in FIG. 7G are logically summed, the falling edge of the horizontal synchronizing signal H21 is masked as shown in FIG. The level continues.

In this case, as shown in FIGS. 7J and 7K, the error voltage V erl becomes high level at the timing of the horizontal synchronization signal H1t, so the oscillation frequency from the VCO 31 increases and the horizontal synchronization signal H21 increases. The period T will be shortened. Thereafter, following the process shown in FIG. 4, the horizontal synchronizing signals H1, H2 and the vertical synchronizing signals (1), (2) become locked. In addition, the dotted line portion shown in FIG. 7B and FIG.
, ■ shows the output state of 2.

In this embodiment, the vertical synchronization signals ■1 and ■2 are 18 or more,
The explanation is based on an example where there is a lead or lag, but if the lead or lag is less than 1H, the horizontal synchronizing signals H1, H
Phase lock is achieved only by comparison of 2.

〔Effect of the invention〕

According to this invention, locking of the horizontal synchronization signal is accelerated by intentionally omitting the horizontal synchronization signal, and the horizontal synchronization signal,
Since the vertical synchronization signal is locked, there is an effect that genlock can be performed quickly and accurately. Also,
Unlike conventional counters, the missing horizontal synchronizing signal speeds up locking of the horizontal synchronizing signal and locks the horizontal and vertical synchronizing signals, which stabilizes the oscillation frequency of the VCO and improves the stability of the VCO. This has the effect that there is no need to have a large counter like . The clock never stops (the timing can always be maintained, and there is no need to stop DRAM, image processing circuits, such as scan converters, A/D converters, D/A converters, etc.). effective.

According to the embodiment, the vertical frequency and horizontal frequency of the graphics data generation circuit are set to the vertical frequency and horizontal frequency of the external video signal, respectively.
Converting to a horizontal frequency has the effect of facilitating superimposition. By compressing the external video signal in high frequencies before A/D conversion, it is possible to display the input signal brightly on the monitor without causing whitewashing even for input signals that are higher than the reference signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of the control circuit shown in FIG. 1, FIG. 3 is a timing chart showing the status of phase comparison, and FIG. Conceptual diagrams showing the concept of phase lock, Figures 5 to 7, respectively.
Each figure is a timing chart illustrating circuit operations corresponding to the phase relationships of vertical synchronization signals. LK: Clock.

Claims (2)

[Claims] (1) In a phase-locked loop circuit that matches the phase of the synchronization signal of the video signal generated by the video signal generation circuit based on the external synchronization signal with the phase of the reference composite synchronization signal, the horizontal synchronization signal of the video signal is a phase comparison circuit that compares the phase of the horizontal synchronization signal of the reference composite synchronization signal with the phase of the horizontal synchronization signal of the reference composite synchronization signal; a VCO that outputs a signal with a frequency corresponding to the output signal of the phase comparison circuit; and a vertical synchronization signal of the video signal. and the phase of the vertical synchronization signal of the reference composite synchronization signal, and the phase difference is 1H.
and a circuit for thinning out one horizontal synchronization signal of the reference composite synchronization signal input to the phase comparison circuit or the synchronization signal of the video signal generated by the video signal generation circuit when the output of the VCO exceeds A phase-locked loop circuit characterized in that the above external synchronization signal is used. (2) A claim in which the composite synchronization signal is separated from an output signal from an external video signal regenerator, and the video signal generation circuit creates graphics data based on the output of the VCO. The phase-locked loop circuit according to item (1).