JPH04288778A - Genlock device - Google Patents

Abstract

PURPOSE:To generate the clock pulse of 13.5MHz locked by a synchronizing signal from an inside synchronizing signal generator and to lock the synchronizing signal and, the clock pulse to an outside signal as well. CONSTITUTION:In an inside genlock mode, a synchronizing signal generator 10 generates the inside synchronizing signal in a free operation mode, a decoder 20 inputs the inside synchronizing signal, and the clock pulse of 13.5MHz locked to the line frequency of the inside synchronizing signal is generated from a clock generator 24. In an outside genlock mode, the decoder 20 inputs an outside synchronizing signal and outputs a synchronizing signal locked to this outside synchronizing signal to the synchronizing signal generator 10, the clock pulse of 13.5MHz locked to the line frequency of the outside synchronizing signal is generated from the clock generator 24, and the synchronizing signal generator 10 generates the inside synchronizing signal locked to the inputted synchronizing signal.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a genlock device,
In particular, the present invention relates to a genlock device that lines-locks a 13.5 MHz clock pulse used in a dual NTSC/PAL digital storage system to the line frequency of internal and external video signals.

0002

2. Description of the Related Art Genlock devices are used in TV equipment where a video signal from an external signal source is applied to a camera system in order to combine it with an internally generated camera signal. be done. Genlock devices typically lock the camera system's internal synchronization signal generator to external signal line and field and color subcarrier signals.

0003

However, when genlocking a camera video signal to an external signal, it is extremely difficult to achieve genlock without causing jitter to both signals. When these signals are used in a digital storage system, the clock pulses for the digital storage system must be closely locked to the synchronization signal of the internal synchronization signal generator.

[0004] If both signals are not locked, a second (another) jitter occurs between the video signals, and the image quality of the monitor image deteriorates due to the jitter. To prevent the occurrence of secondary jitter, the clock pulses for the digital storage system are derived directly from the master oscillator of the internal synchronization signal generator. In the digital system, the so-called D1 format is applied, and a 13.5 MHz clock pulse is used as a sampling pulse, but a special synchronization signal generator is required to obtain this clock pulse.

[0005] This type of internal synchronization signal generator has four
Based on fS (=14.31818MHz), for example, the color subcarrier fS (=3.579545MHz),
Composite synchronization signals such as horizontal synchronization signal HS and vertical synchronization signal VS are generated. The present invention has been made in view of the above circumstances, and is capable of generating a 13.5 MHz clock pulse locked to a synchronizing signal from an internal synchronizing signal generator, and is capable of generating a 13.5 MHz clock pulse locked to the synchronizing signal and the 13.5 MHz clock pulse.
It is an object of the present invention to provide a genlock device capable of locking a Hz clock pulse to an external signal.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention includes a phase-locked loop circuit, in a free running mode or inputting an internal synchronization signal for driving a video device and its digital system. It includes a first synchronization signal generation means that locks to a synchronization signal and generates it, and a phase-locked loop circuit, and receives an internal synchronization signal from the first synchronization signal generation means or an external synchronization signal from an external video device,
A second synchronization signal generating means for generating a 13.5 MHz clock pulse and a synchronization signal locked to the line frequency of the input internal or external synchronization signal, and a switching means for switching between an internal genlock mode and an external genlock mode. , when switched to the internal genlock mode, the first synchronization signal generation means generates an internal synchronization signal in the free-running operation mode, and the second synchronization signal generation means inputs the internal synchronization signal and When the digital system is switched to the external genlock mode by outputting a 13.5 MHz clock pulse locked to the line frequency of the input internal synchronization signal, the second synchronization signal generating means inputs the external synchronization signal. , 13.5 locked to the line frequency of the input external synchronization signal.
A MHz clock pulse is output to the digital system, and the synchronization signal is output to the first synchronization signal generation means, and the first synchronization signal generation means generates an internal synchronization signal locked to the input synchronization signal. It is characterized by

[0007]

According to the present invention, when the switching means switches to the internal genlock mode, the first synchronizing signal generating means generates the internal synchronizing signal in the free-running operation mode, and the second synchronizing signal generating means The means receives the internal synchronization signal and outputs a 13.5 MHz clock pulse locked to the line frequency of the input internal synchronization signal to the digital system. Further, when the switching means switches to the external genlock mode, the second synchronization signal generating means inputs the external synchronization signal and locks to the line frequency of the input external synchronization signal.
A MHz clock pulse is output to the digital system, and a synchronization signal locked to the external synchronization signal is output to the first synchronization signal generation means, and the first synchronization signal generation means receives the input synchronization signal. Generates an internal synchronization signal locked to

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the genlock device according to the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of a genlock device according to the present invention. This genlock device can be switched between an internal genlock mode and an external genlock mode using a mode changeover switch (not shown).

When switched to internal genlock mode, that information is applied to the decoder 20, for example via the IIC bus, and the decoder 20 switches switches S1 and S2 to the positions shown. On the other hand, when the mode is switched to the external genlock mode, the switch S1 is switched to the external signal side including the composite synchronization signal, and the switch S2 is turned on. Next, the case of internal genlock mode will be explained.

In this case, the switches S1 and S2 are in the positions shown, and the synchronizing signal generator 10 generates 4 fS (=14.31818
MHz), a composite synchronization signal such as a color subcarrier fS, a horizontal synchronization signal HS, a vertical synchronization signal VS, etc. is generated. This composite synchronization signal is applied to video processing circuit 30, digital system 40, and switch S1.

The video processing circuit 30 performs appropriate signal processing on the video signal applied from the video camera 32 based on the composite synchronization signal, and outputs the composite video signal to the digital system 40 via the A/D converter 34. . On the other hand, the composite synchronization signal applied to the A/D converter 22 via the switch S1 is converted into a digital signal here, and this digital synchronization signal is applied to the decoder 20. The decoder 20 generates a synchronously fixed 6.15MHz clock,
This is added to the clock generator 24, which in turn connects the digital system 40 and the A/D converter 2.
Generates a 13.5MHz clock pulse for 2. As a result, this clock pulse is locked to the line frequency of the internal synchronization signal. Therefore, in the internal genlock mode, both the camera video signal and the 13.5 MHz clock pulse are locked to the synchronization signal generator 10.

Next, the case of internal genlock mode will be explained. In this case, the switch S1 is switched to the external video signal side including the composite synchronization signal, and supplies, for example, an NTSC system external video signal to the A/D converter 22. Further, the switch S2 is turned on, and the horizontal synchronizing signal HS and the vertical synchronizing signal VS from the decoder 20 are applied to the synchronizing signal generator 10.

The digital external video signal converted into a digital signal by the A/D converter 22 is input to a decoder 20, which then generates a 13.5 MHz clock pulse line-locked to the external signal. The clock generator 24 is driven. Further, the decoder 20 applies the horizontal synchronizing signal HS and the vertical synchronizing signal VS locked to the external signal to the synchronizing signal generator 10 via the switch S2.

The synchronization signal generator 10 compares the frequency and phase of the composite synchronization signal generated based on the 4fS oscillation frequency from the oscillator 12 and the input signal from the decoder 20, and generates an average DC voltage proportional to the error. is applied to the control terminal of the oscillator 12 via the low-pass filter 14, and the frequency of the oscillator 12 is changed in a direction that reduces the error.

Therefore, in the case of external genlock mode,
Camera video signal, synchronization signal generator 10 and 13.5M
The Hz clock pulse is locked to the line rate of the external video signal.

[0016]

As explained above, according to the genlock device according to the present invention, it is possible to generate a 13.5 MHz clock pulse locked to the synchronization signal from the internal synchronization signal generator, and also to generate the synchronization signal and 13
．． The 5MHz clock pulse can be locked to an external signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a genlock device according to the present invention.

[Explanation of symbols]

10...Synchronization signal generator 12...Oscillator 14...Low pass filter 20...Decoder 22, 34...A/D converter 24...Clock generator 30...Video processing circuit 40...Digital system S1, S2...switch

Claims (1)

[Claims] 1. A first synchronization signal generating means that includes a phase-locked loop circuit and generates an internal synchronization signal for driving a video device and its digital system in a free-running operation mode or locked to an input synchronization signal. and a phase-locked loop circuit, inputting an internal synchronizing signal from the first synchronizing signal generating means or an external synchronizing signal from an external video device, and locking to the line frequency of the input internal or external synchronizing signal. .5MHz clock pulse and a synchronization signal, and a switching means for switching between an internal genlock mode and an external genlock mode, and when switched to the internal genlock mode, the first The synchronization signal generation means generates an internal synchronization signal in a free-running operation mode, and the second synchronization signal generation means inputs the internal synchronization signal and generates a 13.5MH MHz signal locked to the line frequency of the input internal synchronization signal.
When the digital system is switched to the external genlock mode by outputting a clock pulse of z to the digital system, the second synchronization signal generating means inputs the external synchronization signal;
1 locked to the line frequency of the input external synchronization signal
A 3.5 MHz clock pulse is output to the digital system, and the synchronization signal is output to the first synchronization signal generation means, and the first synchronization signal generation means generates an internal synchronization signal locked to the input synchronization signal. A genlock device characterized by generating.