JP2789620B2 - Phase locked loop circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit suitable for a genlock circuit.

[Summary of the Invention]

The present invention relates to a phase locked loop circuit for matching the phase of a video signal synchronization signal generated based on an external synchronization signal with the phase of a reference composite synchronization signal. A phase comparison circuit that compares the phase of the horizontal synchronization signal of the composite synchronization signal, a VCO that outputs a signal having a frequency corresponding to the output signal of the phase comparison circuit, a phase of the vertical synchronization signal of the video signal, and a reference composite synchronization Compare the phase of the vertical synchronization signal of the signal, and when the phase difference exceeds 1H, the horizontal synchronization of one of the reference composite synchronization signal input to the phase comparison circuit or the synchronization signal of the video signal generated by the video signal generation circuit A signal thinning circuit is provided.By using the output of the VCO as an external synchronization signal, the horizontal synchronization signal can be locked quickly, and genlock can be performed quickly and accurately. .

[Conventional technology]

For example, when superimposing a computer graphics image on an image reproduced by a VTR, it is necessary to perform a so-called genlock, which synchronizes the synchronization signals of both video signals. Conventional techniques for performing this genlock include the following.

The vertical synchronizing signals are compared with each other, a VCO is oscillated with an error voltage corresponding to the phase difference, a dot clock (hereinafter, referred to as a clock) is formed, and the horizontal synchronizing signal and the vertical synchronizing signal are calculated by counting the clocks. Form.

The horizontal synchronization signals are compared with each other, a VCO is oscillated with an error voltage corresponding to the phase difference, a clock is formed, and the clock is counted to form a horizontal synchronization signal and a vertical synchronization signal.

A device that compares both horizontal and vertical sync signals.
The horizontal synchronizing signal performs a phase comparison, and the vertical synchronizing signal detects the vertical synchronizing signal, operates a counter, and determines the interval between the vertical synchronizing signals by the counter. In this way, the vertical synchronizing signal and the horizontal synchronizing signal are synchronized, and a clock is formed thereafter.

[Problems to be solved by the invention]

 The above prior art has the following problems.

However, since the interval between the vertical synchronization signals is long, there is little chance of error detection, and the stability of the oscillation frequency of the VCO is correspondingly lacking. It must also have a large counter.

 Must have a large counter.

Cannot make timing until the clock is formed by synchronizing the vertical synchronizing signal and the horizontal synchronizing signal. During that time, the DRAM and the circuits for image processing, for example, the scan converter, the A / D converter, the D / A converter, and the like must be stopped.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a phase locked loop circuit that can perform genlock quickly and accurately.

[Means for solving the problem]

The present invention relates to a phase locked loop circuit for matching the phase of a video signal generated by a video signal generation circuit based on an external synchronization signal to the phase of a reference composite synchronization signal, And a VCO that outputs a signal of a frequency corresponding to the output signal of the phase comparison circuit, and a phase of the vertical synchronization signal of the video signal. ,
Compare the phase of the vertical synchronizing signal of the reference composite synchronizing signal, and when the phase difference exceeds 1H, the reference composite synchronizing signal input to the phase comparing circuit or the synchronizing signal of the video signal generated by the video signal generating circuit. A circuit for thinning out one horizontal synchronizing signal is provided, and the output of the VCO is used as an external synchronizing signal.

[Action]

The phase comparison circuit compares the phase of the horizontal synchronization signal of the video signal generated by the video signal generation circuit based on the external synchronization signal with the horizontal synchronization signal of the reference composite synchronization signal.
If the phase difference exceeds 1H, one of the reference composite synchronizing signal or the synchronizing signal of the video signal is thinned out.

As a result, the level of the voltage supplied to the VCO changes, and a signal having an oscillation frequency corresponding to the voltage level is output. Since the VCO oscillation output is used as an external synchronization signal,
The cycle of the video signal synchronization signal changes based on the external synchronization signal. Eventually, the synchronization signal of the video signal is locked to the phase of the reference composite synchronization signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. This embodiment uses a Genlock for a superimposer that adds a computer graphics video signal to a reproduced composite video signal.
The present invention is applied to a circuit.

An external video signal SV1 is supplied to a terminal 1 shown in FIG. The external video signal SV1 is supplied to the RGB decoder 2 and the synchronizing signal separating circuit 3, respectively.

The external video signal SV1 is converted into RGB, R, G,
The signal is decomposed into B primary color signals. Each primary color signal is supplied to a high-frequency compression circuit 4 and subjected to high-frequency compression. Due to this high-frequency compression, even an input signal equal to or more than the reference signal does not suffer from overexposure and can be displayed brightly on a monitor. Then, this primary color signal is supplied to the A / D converter 5 and is 18 bits [R,
G and B are each a 6-bit digital signal. This digital signal is supplied to the scan converter 6, and the horizontal scanning frequency is changed from 15.75KHz by a line memory, for example.
Converted to 31.5KHz. Then, it is supplied to the switching circuit 7.

On the other hand, the 8-bit graphics data output from the graphics data generating circuit 8 is
And the 1-bit control data output from the graphic data generation circuit 8 is supplied to the key signal generator 10. The graphics data is converted from 8 bits to 18 bits by the color pallet 9 and is switched by the switching circuit 7.
Supplied to The control data is stored in the key signal generator 10
Is converted into a control signal for controlling the switching circuit 7. This control signal is supplied to the switching circuit 7 and controls the switching circuit 7.

The digital signal supplied from the scan converter 6 and the graphics data supplied from the color palette 9 are switched by the switching circuit 7. After that, an 18-bit digital signal or 18-bit graphics data is supplied to the D / A converter 11 and is supplied to the monitor 12 as an analog video signal.

The external video signal SV1 is supplied to the synchronizing signal separation circuit 3, where the vertical synchronizing signal V1 and the vertical signal H1 are separated and supplied to the control circuit 13, respectively. Also, the vertical synchronizing signal V2 and the horizontal synchronizing signal H2 are formed by dividing the frequency of the clock CLK from the above-mentioned graphics data generating circuit 8 and supplied to the control circuit 13.

As shown in FIG. 2, the horizontal synchronizing signal H1 is
Are supplied to a field discriminating circuit 21, a first mask pulse generating circuit 22, a second mask pulse generating circuit 23, and further to an OR gate 24.

The vertical sync signal V1 is applied to the field determination circuit via terminal 25.
21, is supplied to the vertical phase comparison circuit 26. On the other hand, the horizontal synchronizing signal H2 is supplied to a 1/2 frequency dividing circuit 27 via a terminal 26, and the vertical synchronizing signal V2 is supplied to a vertical phase comparing circuit 26 via a terminal 28.

The vertical synchronizing signal V1 and the horizontal synchronizing signal H1 are supplied to a field discriminating circuit 21 to discriminate whether the field is an odd field or an even field. The output signal from the field determination circuit 21 is supplied to a vertical phase comparison circuit 26,
The vertical phase comparison circuit 26 is controlled.

The vertical synchronization signals V1 and V2 are compared in phase by the vertical phase comparison circuit 26. If there is a phase difference of 1H or more, the output signal SΔV is supplied to the first mask pulse generation circuit 22 and the second mask pulse generation circuit 23.

The horizontal synchronization signal H2 shown in FIG. 3B is formed by dividing the horizontal synchronization signal H2 shown in FIG. 3A by half. The horizontal synchronization signal H20 is supplied to the first mask pulse generation circuit 22,
The signal is supplied to the second mask pulse generation circuit 23 and further to the OR gate 28.

The output signal SΔV activates the first and second mask pulse generation circuits 22 and 23, respectively, and the first and second mask pulse generation circuits 22 and 23 output the mask pulse PM1 based on the horizontal synchronization signals H1 and H20. , PM2 are formed. The mask pulses PM1 and PM2 are output to the OR gates 24 and 28.

The mask pulse PM1 from the first mask pulse generation circuit 22
Then, the horizontal synchronizing signal H1 is ORed by the OR gate 24, and becomes the horizontal synchronizing signal H11. This horizontal synchronization signal H11
Is supplied to the horizontal phase comparison circuit 29.

The mask pulse PM2 from the second mask pulse generation circuit 23
Then, the OR of the horizontal synchronizing signal H20 is obtained by the OR gate 28 to obtain the horizontal synchronizing signal H21. This horizontal synchronization signal H21
Is supplied to the horizontal phase comparison circuit 29.

The horizontal synchronizing signals H11 and H21 from the OR gates 24 and 28 are supplied to a horizontal phase comparison circuit as shown in FIGS. 3B and 3C.
At 29, the phases are compared at the falling edge, an error voltage Ver1 is formed in accordance with the phase difference, and supplied to the VCO 31 via the low-pass filter 30.

The concept of the above-mentioned phase comparison and phase lock is shown in FIG. That is, the horizontal synchronization signal H21 shown in FIG.
When there is a phase difference between the horizontal synchronization signal H11 shown in FIG. 4B and the horizontal synchronization signal H11 shown in FIG. 4B, the horizontal synchronization signal H11 shown in FIG. 4C and FIG. As shown, the period T of the horizontal synchronizing signal H21 increases, so that the error voltage Ver1 becomes low level, and the input voltage Ver2 of the VCO 31
And the oscillation frequency of the VCO 31 also decreases. Eventually the phase difference between the horizontal synchronization signals H21 and H11 is gradually reduced,
The input voltage Ver2 of the VCO 31 increases, and the oscillation frequency of the VCO 31 also increases. As a result, the horizontal synchronizing signals H1, H2,
V1 and V2 are phase-locked.

In this way, by masking one of the horizontal synchronization signals H11 and H21 and intentionally missing it, the horizontal synchronization signals H1, H2,
The phase lock of the vertical synchronization signals V1 and V2 can be accelerated,
Genlock can be performed quickly and accurately. Since the phase lock of the horizontal synchronization signals H1 and H2 and the vertical synchronization signals V1 and V2 can be accelerated, the oscillation frequency of the VCO 31 can be stabilized. Furthermore, there is no need to have a large counter as in the past, and DRAM, scan converters, A / D
It is not necessary to stop the converter, the D / A converter, and the like.

An oscillation output signal is formed by the VCO 31 according to the input voltage Ver2, and is used as a clock CLK. This clock CLK is applied to terminal 32
Is returned to the graphics data generation circuit 8 via

From the control circuit 13, the vertical synchronizing signal H2, the horizontal synchronizing signal V2
Is supplied to the monitor 12. The above-described analog video signal is controlled by the vertical synchronizing signal H2 and the horizontal synchronizing signal V2, and is displayed on the monitor 12.

By the way, the external video signal SV1 from the VTR has a vertical frequency of 60 Hz and a horizontal frequency of 31.5 KHz, while the graphics data from the graphics data generating circuit 8 has a vertical frequency of 70 Hz and a horizontal frequency of 31.5 KHz. is there. Therefore, by adding computer graphics rasters above and below the screen of the monitor 12, the vertical frequency of the graphics data is 60 Hz and the horizontal frequency is 31.5 KH.
has been converted to z. The conversion of the vertical frequency and the horizontal frequency facilitates superimposition. In addition, since the conversion increases the number of rasters, for example, a simple change of the parameter changes a circle into a horizontally long ellipse. Therefore, the clock frequency of the graphics data generating circuit 8 is increased (approximately 10%) by an amount corresponding to the horizontal width.

There are the following three types of phase relationship between the vertical synchronization signals V1 and V2.

(A) When the vertical synchronizing signals V1 and V2 have the same phase FIGS. 5A and 5C show the horizontal synchronizing signals H1 and H2.

As shown in FIGS. 5B and 5D, when the vertical synchronization signals V1 and V2 are in phase, there is no output signal SΔV as a vertical phase error as shown in FIG. 5E. Therefore,
As shown in FIGS. 5F and 5G, the mask pulses PM1 and PM2 are not output. Therefore, FIG. 5H and FIG.
The falling edges of the horizontal synchronization signals H11 and H21 shown in FIG. I are not masked, and neither the error voltage Ver1 nor the input voltage Ver2 is output as shown in FIGS. 5J and 5K. In this state, the oscillation frequency from VCO 31 is a free-run frequency. The dotted lines shown in FIGS. 5B and 5D show the output states of the vertical synchronization signals V1 and V2 in odd fields.

(B) When the vertical synchronizing signal V1 leads the vertical synchronizing signal V2 by 1H or more, as shown in FIG. 6B and FIG. 6D, the vertical synchronizing signal V1 is When the signal has advanced by 1H or more, as shown in FIG. 6E, the output signal S.DELTA.V is at a high level from the fall of the vertical synchronization signal V1 to the fall of the vertical synchronization signal V2. As a result, only the mask pulse PM1 is set to the high level at the timing shown in FIG. 6F. When the logical sum of the horizontal synchronizing signal H1 and the mask pulse PM1 shown in FIG. 6F is obtained, the falling of the horizontal synchronizing signal H11 is masked as shown in FIG. Levels continue.

In this case, as shown in FIGS. 6J and 6K,
Error voltage Ver at falling timing of horizontal synchronization signal H21
Since 1 becomes low level, the oscillation frequency from the VCO 31 decreases, and the period T of the horizontal synchronization signal H21 increases.
Subsequently, the horizontal synchronization signals H1 and H2 and the vertical synchronization signals V1 and V2 are locked by following the progress as shown in FIG. 6B and 6D show the output states of the vertical synchronizing signals V1 and V2 in the odd field.

(C) When the vertical synchronization signal V1 is delayed by 1H or more with respect to the vertical synchronization signal V2 As shown in FIGS. 7B and 7D, the vertical synchronization signal V1 is When the delay is 1H or more, as shown in FIG. 7E, the output signal S.DELTA.V is at a high level from the falling of the vertical synchronizing signal V2 to the falling of the vertical synchronizing signal V1. As a result, only the mask pulse PM2 is set to the high level at the timing shown in FIG. 7G. The horizontal synchronizing signal H20 and the mask pulse PM2 shown in FIG.
Is ORed, the falling of the horizontal synchronizing signal H21 is masked as shown in FIG.
High level is continued.

In this case, as shown in FIGS. 7J and 7K,
Since the error voltage Ver1 goes high at the timing of the horizontal synchronization signal H11, the oscillation frequency from the VCO 31 increases, and the cycle T of the horizontal synchronization signal H21 is reduced. Hereinafter, the fourth
Following the course shown in the figure, the horizontal synchronization signals H1, H
2. The vertical synchronization signals V1 and V2 are locked.
The dotted lines shown in FIGS. 7B and 7D indicate the output states of the vertical synchronization signals V1 and V2 in the case of an odd field.

In this embodiment, the case where the vertical synchronization signals V1 and V2 are 1H or more, leading or lagging is described as an example, but if the leading or lagging is less than 1H, only the comparison of the horizontal synchronization signals H1 and H2 is performed. Phase locking is performed.

〔The invention's effect〕

According to the present invention, the locking of the horizontal synchronizing signal is accelerated by intentionally dropping the horizontal synchronizing signal, and the horizontal synchronizing signal and the vertical synchronizing signal are locked, so that the genlock can be performed quickly and accurately. is there. In addition, the lack of a horizontal synchronization signal, regardless of the counter, speeds up the locking of the horizontal synchronization signal and locks the horizontal synchronization signal and the vertical synchronization signal.
This has the effect that the oscillation frequency of O is stable and it is not necessary to have a large counter as in the prior art. In addition, the clock does not stop, the timing can be always taken, and there is no need to stop the DRAM, the circuit for image processing, for example, the scan converter, the A / D converter, the D / A converter, etc. There is.

According to the embodiment, by converting the vertical frequency and the horizontal frequency of the graphics data generation circuit into the vertical frequency and the horizontal frequency of the external video signal, there is an effect that the superimposition becomes easy. Then, by externally compressing the external video signal before A / D conversion, it does not cause overexposure even for input signals that are higher than the reference signal.
There is an effect that the image can be displayed brightly on the monitor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of the control circuit shown in FIG. 1, FIG. 3 is a timing chart showing the state of phase comparison, and FIG. FIGS. 5 to 7 are conceptual diagrams showing the concept of phase lock, respectively.
The figure is a timing chart for explaining the circuit operation corresponding to the phase relationship of the vertical synchronization signal. Explanation of main reference numerals in the drawings 8: graphics data generation circuit, 13: control circuit, 29: horizontal phase comparison circuit, 31: VCO, SV1: external video signal, H1,
H2, H20, H11, H21: horizontal synchronization signal, V1, V2: vertical synchronization signal, CLK: clock.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsumi Tatsumi 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-62-82773 (JP, A) JP-A Sho 62-26980 (JP, A) JP-A-62-250772 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/073

Claims (2)

(57) [Claims] 1. A phase locked loop circuit for matching a phase of a video signal generated by a video signal generation circuit based on an external synchronization signal with a phase of a reference composite synchronization signal. A phase comparison circuit that compares the phase of the synchronization signal with the phase of the horizontal synchronization signal of the reference composite synchronization signal; a VCO that outputs a signal having a frequency corresponding to the output signal of the phase comparison circuit; The phase of the synchronizing signal is compared with the phase of the vertical synchronizing signal of the reference composite synchronizing signal, and when the phase difference exceeds 1H, the reference composite synchronizing signal or the video signal generating circuit input to the phase comparing circuit. A circuit for thinning out one of the horizontal synchronizing signals of the generated video signal synchronizing signal, wherein the output of the VCO is used as the external synchronizing signal. 2. A composite synchronizing signal separated from an output signal from an external video signal reproducer, wherein the video signal generating circuit generates graphics data based on an output of the VCO. The phase-locked loop circuit according to claim 1.