JPH02146682A - Method and device for inspecting pattern defect - Google Patents

Abstract

PURPOSE:To efficiently detect a true defect in an inspection pattern by setting an inspection object part and a non-inspection part according to the inspection pattern and forming a comparison pattern for masking the non-inspection part. CONSTITUTION:The inspection object part and the non-inspection part are set according to the inspection pattern, the first comparison pattern A for masking the non-inspection part is formed, the first comparison pattern is A is compared with the inspection pattern B, and the difference information obtained by the comparison is taken out as the first defect information C. Further, the second comparison pattern D for setting a defect allowable area to the first defect information is formed based on the first comparison pattern A, and the first defect information C existing in an area except the defect allowable area is detected as the defect. Thus, only the true defect in the inspection pattern can be efficiently detected.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a pattern defect inspection method and apparatus for determining defects in figures and wiring patterns, and in particular to a pattern defect inspection method and apparatus for determining defects in figures and wiring patterns, and in particular, detecting defects by comparing a pattern to be inspected with a mask pattern. The present invention relates to a pattern defect inspection method and apparatus for detecting pattern defects.

(Prior art) As a defect inspection device that detects defects such as chips and protrusions in wiring patterns, an inspection pattern on an object to be inspected and a wiring pattern without defects (hereinafter referred to as "master pattern") are each detected using an imaging device. Convert the video signal to 2
It has been proposed in the past to detect defects by converting into values and comparing the respective binarized signals corresponding to the values (for example, Japanese Patent Application Laid-Open No. 62-272379).
.

According to this conventional inspection apparatus, either the inspection pattern or the mask pattern is enlarged and reduced as shown in FIG. 6 to extract the respective outlines. (The broken line indicates the outline of the reduced pattern), when there is a wiring pattern on the outline 1- of the enlarged pattern (portion P in the same figure), and when there is a wiring pattern on the outline 1- of the enlarged pattern, and when there is a wiring pattern on the outline 1- of the reduced pattern, (i.e., parts other than the wiring pattern) (part Q in the same figure), these June), Q
It is efficient to use the photo block data as master pattern data for comparison with the inspection pattern, but normally this photo block data does not include holes for inserting parts. - Mask pattern data read from a mask film for producing a printed circuit board that is divided into stages without using CAD includes holes for inserting parts. In addition, there are cases where the object to be inspected is before the holes are made, and there are cases where it is after the holes are drilled.
Four cases (cases ① to ①) occur.

On the other hand, the above-mentioned conventional defect inspection apparatus assumes that the inspection pattern and the mask pattern have a gap between the parts other than the defective part. In case I11, the absence of holes is incorrectly determined to be a defect even though it is normal for the board to have no holes in the board before drilling.

The present invention has been made to solve such problems, and a portion that loses its function as a wiring pattern is determined to be a defect. As a result, small defects that do not fall within the enlarged or reduced contour line are not detected, and only relatively large defects are detected.

(Problem to be solved by the invention) During actual pattern defect inspection, the inspection pattern or mask pattern may or may not have a hole for inserting a component, so depending on the combination of these, the following four cases may occur. Occurs.

Case ■: There is a hole in both the inspection pattern and the mask pattern Case ■: There is a hole in the inspection pattern. If there are no holes in the master pattern, Case IJI: There are no holes in the inspection pattern. When there is a hole in the master pattern Case ■: When there is no hole in both the inspection pattern and the mask pattern For example, when there is a hole in the master pattern
In the case of a pattern divided by steps (referred to as A, D J), data for the Fu-Ai block (binarized data) is created at the time of crotch pulling, so small irregularities that will never occur are not detected. It is an object of the present invention to provide a pattern defect inspection method and apparatus that can efficiently detect only true defects in an inspection pattern, regardless of the presence or absence of a component insertion hole in the inspection pattern or mask pattern. shall be.

(Means for Solving the Problems)"--In order to achieve the above objects, the present invention. The master pattern and the inspection pattern on the object to be inspected are captured by the imaging means.
In a pattern defect inspection method that compares the converted information and determines the defect of the inspection pattern based on the comparison result, a portion to be inspected and a non-inspection portion are set according to the inspection pattern, and the non-inspection portion is masked. A first comparison pattern is formed to compare the first comparison pattern and the inspection pattern, and the difference information is extracted as first defect information. 1
A second comparison pattern is formed to set a defect tolerance area in the defect information of the defect information, and the first defect information located in an area other than the defect tolerance area is detected as a defect.
In a pattern defect inspection device that compares a master pattern with information obtained by binarizing an inspection pattern on an object to be inspected using an imaging means and determines defects in the inspection pattern based on the comparison results, Inspection 1
a first comparison pattern forming means for setting an image area and a non-inspection area and forming a first comparison pattern for masking the non-inspection area; and comparing the first comparison pattern and the inspection pattern. a first defect information generating means for extracting the difference information as first defect information; and a second comparison pattern for setting a defect tolerance area in the first defect information described in 01j based on the first comparison pattern. and the second defect information generating means that detects the first defect information in an area other than the defect tolerance area as a defect.

(Function) The hole for pushing the °C component is masked by the first comparison pattern, and only defects detected in areas other than the defect tolerance area set by the second comparison pattern are detected (hereinafter referred to as "hole data") The mask pattern data is supplied to the mask pattern generation circuit 5, and the hole data is supplied to the pad pattern generation circuit 6 according to a command from the first CPU. ” 1. As master pattern data,
For example, CAD pattern data for photo blocks,
Alternatively, pattern data read from a mask film for substrate production is used. Note that the pattern data created with OA+ does not include holes for inserting l'fli products as data, whereas the pattern data read from the mask film includes holes for inserting parts as data. It is.

The mask pattern generation circuit 5 is a circuit for demodulating (returning to an uncompressed state) the master pattern data stored in the external storage device 2, which is compressed to save memory capacity. , a first memory (so-called first-in-first-out memory, hereinafter referred to as rF IFO) from which data is read in the order in which it is written.
The compressed data is stored in the memory j) 51 and the second CPU 52.

(Embodiment) An embodiment of the present invention will be described below based on the accompanying drawings.

FIG. 1 is a block diagram of the main parts of the pattern defect inspection apparatus according to the present invention. In the figure, 1 is a first central processing unit (r CP tJ J), External storage device 2 and . A drive device for an X, -Y table (not shown) connected to the master pattern generation circuit 5 and the pad pattern generation circuit 6, and further mounting the first and second synchronous delay circuits 10.15 and the substrate to be inspected. Connected to 3.

The first CPU stores the pattern data stored in the external storage device 2. Transfer (write) control to the master pattern generation circuit 5 and pad pattern generation circuit 6, timing control of pattern data by the synchronous delay circuits 10 and 1.5, and <xy table position control based on the pattern data are performed. The external storage device 2 stores pattern data. It is composed of master pattern data, an IC 53 for demodulating hole positions and hole diameters for component insertion, a first auxiliary memory 54, and a second FIFO memory 55. here,
WR is a write command, R1 is a read command.

IN indicates an interrupt signal, and interrupt signal NT is a signal for notifying the first CPU of a delay in data transfer in the FIFO memory or the occurrence of an error.

Master pattern data from the external storage device 2 is input to the first FIFO memory 51 based on a write command from the first CPU, and the mask pattern data is input to the first FIFO memory 51 based on a read command from the compressed data demodulation IC 53. The signal is input to the IC 53 according to the following.

The compressed data demodulation IC 53 is connected to the second CPU 52 and the first auxiliary memory 54, and the second C)) U
52, the input compressed pattern data is demodulated using the first auxiliary memory 54, and the demodulated pattern data is input to the second FIFO memory 55.

The output of this second FIFO memory 55 is the output of the mask pattern generation circuit 5, that is, as mask pattern data.
The first υ1 other music OR circuit (hereinafter r IE
circuit).

The pad pattern generation circuit 6 is a circuit that generates a pad pattern (see (b) of FIG. 3(a) to be described later) corresponding to a predetermined area centered on the hole position for inserting the component based on the hole data. Yes, there is a third FIFO memory 61, a third CI) U62, etc., a graphic display controller I
・Roller 63, second auxiliary memory 64, and fourth F■
FO memory 65.

The hole data from the 0; Graphic display controller 6
3 is input. The third CPU 62 uses a third FIFO
The hole data outputted from the memory 61 is divided into 1,200, and reading and writing of the hole data to the graphic display controller 63 is controlled. The graphic display controller 63 is a circuit that generates a pattern in an area where pattern defects are not detected (defect tolerance area, hereinafter referred to as "mask area") by performing hole data and graph minor processing, etc. It is constituted by a number of line memories 91 according to the degree and a mask area determination circuit 92. The output side of the window processing circuit 8 is connected to the input side of the first line memory 9, and the (i-1)th line memory 91 is connected to the input side of the first line memory 91. The output side of is connected (however, 1-2
~No), the output sides of all line memories 91 are connected to a mask area determining circuit 92.

The mask area determining circuit 92 determines a mask area based on input data from the line meter 91, and inputs the determined mask area to the mask circuit 16 as mask pattern data (second comparison pattern data).

0 (J) The first synchronization delay circuit 10 is a delay circuit for synchronizing the output data of the window processing circuit 8 and the inspection pattern data of the board to be inspected, which will be described later. The output data display of this first synchronous delay circuit 1.0 is controlled by CPIJ.
(The operator can set the pad shape to
(set according to IV), pad pattern data is created using the second auxiliary memory 64, and the created data is input into the fourth Fl, FO memory. 4th FT
The output of the FO key is output from the pad pattern generation circuit 6, that is, the EXOR circuit 7 as pad pattern data.
is input.

The E ljN path 8.

The window switching device S is a device that switches pattern data to the bypass circuit S' side without inputting the pattern data to the window processing circuit 8 in response to a command from the first CPU. The window processing circuit 8 performs window processing, which will be described later, and inputs its output data to the mask pattern generation circuit 9 and the first synchronous delay circuit 10.

The mask pattern generation circuit 9 performs the expansion/reduction described later in the first
The data is input to the second EX○R circuit 14 as comparison pattern data.

The CCI) camera 11 detects the second pattern of the X-Y table "substrate to be inspected" 2 as an optical signal, converts it into an electrical signal, and inputs it to the sensitivity correction circuit 12 as inspection pattern data. The sensitivity correction circuit 12 performs one-novel correction on the test pattern data (analog signal) and inputs the corrected test pattern data to the binarization circuit 13 . The binarization circuit 13 converts the input inspection pattern data into a binarization signal (
In this embodiment, the wiring pattern portion of the board to be inspected is converted into a signal whose value is O1 (signal whose base portion is set to value 1), and the binarized inspection pattern data is input to the second EX-OR circuit I4. .

The second (7) IE The signal is input manually to the mask circuit 1G via the second synchronous delay circuit j5. The second synchronization delay circuit 15 is a delay circuit for synchronizing the mask pattern data from the mask pattern generation circuit 9 and the first defect information, that is, the output data of the second EX-OR circuit I4. Yes, and controlled by the first CI) U. The mask circuit 16 performs an AND operation on two input data, that is, mask pattern data and first defect information, and outputs the result of the operation as final defect information (second defect information).

In this embodiment, the CCD camera 11. Sensitivity correction circuit 12. and the binarization circuit 13 constitute an imaging means,
1st CI”U], external storage device 2° mask pattern generation circuit 5. pad pattern generation circuit 6. 1st E
X-OR circuit 7. and the window processing circuit 8
The comparison pattern forming means is configured, and the j-th CPUI,
First synchronous delay circuit 10. and the second EX, -01
The length circuit 1/l constitutes a first defect information generating means. The master pattern generating circuit 9 constitutes a second comparison pattern forming means, and the first CPU, the second synchronization delay circuit 15, and the mask circuit 1G generate the second defect information.
(A) to (R) in FIG. 3 correspond to the same reference numerals in FIGS. 1 and 2. FIG.

In addition, the part indicated by the cross hatch in Fig. 3 (hereinafter referred to as the "black part") has the value 1 of the binary data, and the other part (
(hereinafter referred to as "white parts") correspond to the value O, respectively.

FIG. 3(a) shows an example of the above-mentioned case (2), that is, a case where both the mask pattern and the inspection pattern have holes for inserting parts. In this case, a black and white checkered pattern as shown in the same figure (b) is created as a pad pattern based on the hole data (pad pattern generation circuit 6).
, the pad pattern (b) and . Exclusive OR 41 (
(hereinafter referred to as rEX-OR operation) is performed (first
The EX-OR circuit 7), Z(7) EX-OR operation is
For inputs of (1,]) or (0,0), set the value O to (
The generating means is constituted by an operation that outputs a value 1 for inputs of L, O) or (0, l), that is, an operation that outputs different parts of two input patterns as a value 1.

In addition, the symbols (a) to (d) and (ch) to (l) in Figure 1 are as follows:
These correspond to the same reference numerals in FIGS. 2 and 3, which will be described later.

Next, the operation of the pattern defect inspection apparatus shown in FIG. 1 will be explained with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing the contents of data processing sent to the pattern defect inspection apparatus of FIG. 1, and each block is indicated by the corresponding reference numeral in FIG. 1. The enlargement processing circuit 901 and the reduction processing circuit 902 of the mask pattern generation circuit 9 are connected to the line memory 91.
and a part of the mask area determination circuit 92, and the third
The IEXOR circuit 903 and the inversion circuit 90/I are included in the mask area determination circuit 92. Enlargement processing circuit 901
The output data of the reduction processing circuit 902 is
The data is input to an OR circuit 903, and the output data of the third EX-OI history circuit 903 is inverted by an inversion circuit 904 and output as mask pattern data. FIG. 3 shows the patterns in each part of FIG. 2 when detecting a defect in a typical example wiring pattern including a hole for inserting a component. In this example, since the black part corresponds to the value 1 and the white part corresponds to the value O, the result of this EX=OR operation is (black,
The pattern (c) in the same figure is obtained, with the part (black) or (white, white) being white, and the part (white, black) being black.

Next, the window switching device S of FIG. 1 is connected to the first CPU
It is connected to the window processing circuit 8 side by the command of (
Window processing is performed only on part B of c), that is, the pad pattern part, to obtain the first comparison pattern (d). FIG. 4 is a diagram showing the principle of this window processing, and the window processing circuit 8 includes, for example, three line memories 401 and a 3×3
It is composed of a two-dimensional memory 402 for pixels and an OR circuit 403. The line memory 401 is composed of the same number of storage elements as the number of pixels in the horizontal direction (i.e., CC]) (scanning direction of the camera 11) of the pattern data signal, and the pattern data is input to the input side (left end) in synchronization with a predetermined synchronization signal. It sequentially moves from there to the output side (right end). The pattern data output from each line memory 401 is stored in the two-dimensional memory 4 of that stage.
02 and the line memory 401 of the next stage. 2
The dimensional memory 402 stores a two-dimensional pattern of 3×3 pixels, and by sequentially moving the pattern data for each pixel from the line memory 401 from left to right in synchronization with the synchronization process, Two-dimensional patterns are sequentially stored in a size of 3×3 pixels. The OR operation circuit 403 has 2
Perform a logical sum operation on all pixel data of Dimensional Memo January 02,
Outputs white only when all pixels are white (value O), and outputs white only when all pixels are black (value O).
When there is a pixel with value J), black is output. Therefore, 3
If white and black pixels coexist within the range of ×3 pixels, 3 ×
All three pixels become black.

The series of examples are for 3×3 pixels, but by increasing the number of line memories and the memory capacity of the two-dimensional memory, window processing can be performed for an arbitrary N×N pixel range.

Referring again to FIG. 2 and FIG. 3(a), the first comparison pattern (d) is input to the second EXOR circuit 14, and is combined with the test pattern shown in pattern (su). EX of
-OR operation is performed to obtain first defect information (nu). Here, in the case of inspection, if there is even one black pixel within the 3 x 3 pixel range, all 3 x 3 pixels are output as black, so the black part is enlarged. In the case of reduction processing, if there is even one white pixel within the 3×3 pixel range, all 3×3 pixels are output as self, so the black portion is reduced. This enlarging/reducing process can also target any NXN pixels like the window processing described above, and the degree of enlarging/reducing changes depending on N, so it depends on the degree (size) of the defect you want to detect. N is set.

Returning to FIG. 3(a), by performing an EX-OR operation on the enlarged pattern (e) and the reduced pattern (e) (third EX-OR circuit 903),
) is obtained, and this is further inverted (inversion circuit 904)
As a result, a mask pattern (second comparison pattern) (d) is obtained.

Next, the + of the first comparison pattern and the test pattern is
? , shows an example in which there are relatively small defects x1 to X4 that do not need to be detected (that is, they do not affect the quality of the substrate to be inspected) and relatively large defects y1 to y1 that should not be detected.

In addition, the - dotted chain line of the first defect information (nu) shows the outline of the inspection pattern (su) for reference, and in reality only the black part is output as the value l, and the other parts are Value O(
white).

On the other hand, the first comparison pattern (d) is the enlargement processing circuit 901
A pattern (E) is obtained by enlarging the pattern (E), and a pattern (E) is obtained by a reduction processing circuit 902 at the same time. Here, enlarging/reducing means enlarging/reducing the black (value 1) portion, and FIG. 5 shows the principle of the enlargement/reduction processing circuit.

501 and 502 in Figure 5 are respectively 401 and 402 in Figure 4.
This is the same line memory and two-dimensional memory as in the window processing, and the enlarged output is obtained by a logical sum operation of all pixel data, and the reduced output is obtained by a logical AND operation of all pixel data. That is, defect information (ru) for the enlargement process is obtained. In this second defect information (L), the dashed line represents the outline of the mask pattern (H), and the dashed line represents the inspection pattern (H).
The hatched area shows the defect detection area (area other than the mask area) for reference, and the actual defect information includes the comparatively large defects y1 to y4.
The pattern in the overlapping area of the hatched area is output as black (value 1), and the other areas are output as white (value O).

As a result, relatively small defects x1 to x4 that do not affect the quality of the board to be inspected are masked by the mask pattern (h), and relatively large defects y1 to y4 that cause quality deterioration of the board are reliably detected. This allows you to reduce unnecessary re-inspection time and labor and accurately identify only true defects.

The above has described an example in which the pad pattern (b) in FIG. 3(a) is subjected to window processing and the pattern (d) is used as the first comparison pattern to obtain the first defect information. Another embodiment in which the pad pattern is used as it is will be described below with reference to FIG.

Figure 7 shows the same case as Figure 3(a) in Case 2, where both the master pattern and the inspection pattern have holes for inserting parts, and the window switching device S in Figure 1 is moved to the first C.
I) U] shows the processing contents when connected to the bypass circuit S' side. The processing up to the state (c) in FIG. 7 is the same as the processing up to (c) in FIG. 3(a), but in FIG. EX-OR operation is performed on the inspection pattern (su) as the first comparison pattern to obtain the defect information.As a result, the pattern (nu) is obtained as the first defect information.

On the other hand, the pattern (C) is enlarged by the enlargement processing circuit 901 to obtain the pattern (E), and at the same time, the pattern (C) is subjected to reduction processing by the reduction circuit 902 and the pattern (E) is obtained.

Next, the enlarged pattern (E) and the reduced pattern (
Perform EX-OR operation with (3rd EX-01
In addition, pattern (1.) is obtained by circuit 903),
Furthermore, by inverting this (inversion circuit 904), the diameter is expanded, and in the reduced pattern (to), all the patterns become self, and the diameter is reduced. If a checkered striped pattern is used as the pad pattern in this way, the mask IJ method for defects around the hole can be arbitrarily selected.

FIG. 3(b) shows an example of the case IJ, that is, a case where the mask pattern does not have a hole for inserting a component, but the board to be inspected has one. In this case, use the pad pattern shown in FIG.
”= An OR operation is performed, and by window processing the B part of the operation result (c), the first comparison pattern (
D) is obtained.

This comparison pattern (d) is the same as (d) in FIG. 3(a).

On the other hand, since the board to be inspected has holes for inserting components, the pattern to be inspected is also the same as that shown in (a) of FIG. 3, for example. Therefore, patterns (d) to (l) in case II
is the same as case (2) (patterns (E) to (R) are not shown), and the final defect information (R) is obtained in the same way as case (2).

Thus, a mask pattern (second comparison pattern) (d) is obtained.

Next, the mask pattern and the first defect information (nu) in the form of black and white stripes in the center obtained by 0 (a set of the first comparison pattern (c) and the inspection pattern (su)) -OR operation are obtained. (
A logical product operation with (d) is performed, and second defect information (l) is obtained as the final defect information. The area other than the shaded area of the second defect information (R) is an area where defects are masked (non-inspection area).

In particular, 1411 minutes indicated by C corresponds to the white portion C of the pattern (H) and serves as a mask for the defect of the hole ff++, which is selected by the "outer diameter of the pad pattern (B)" method.

Therefore, by arbitrarily setting the outer diameter of the pad pattern (B), a defect mask for the hole can be set, and defects around the hole in the second defect information (R) can be selected.

Pattern (c) obtained by enlarging/reducing pattern (c)
In E) and (F), due to the enlargement/reduction process, the checkered striped pattern of the pad pattern (B) becomes completely black in the enlarged pattern (E), just like this. Even if there are no holes in the master pattern and holes in the inspection pattern,
Only true defects can be accurately identified without detecting holes in the inspection pattern as defects.

In this case H, even if the window processing 8 is bypassed and pattern (c) in FIG. 3(b) is used as the first comparison pattern, the results shown in FIGS. The same pattern is obtained, and final defect information can be obtained in the same manner as the example of FIG.

FIG. 3(c) shows an example of case III, that is, a case where a hole for inserting a component exists in the mask pattern but not in the inspection pattern. In this case, use the pad pattern shown in the same figure (b) to create an Ex
-OR operation is performed and pattern (c) is obtained. Next, 13 parts of the pattern (C) are subjected to window processing, but the B part remains almost unchanged, resulting in a first comparison pattern (D) that is substantially the same as the pattern (C). This first comparison pattern (D) is enlarged to form a pattern (E), and reduced to pattern (to) (Due to the reduction process, the black part near the center of the first comparison pattern (D) disappears) is obtained. Furthermore, the EXOR operation of patterns (E) and (D) and the inversion process of the result (1.) of the operation are performed, and a second comparison pattern (H) is obtained.

On the other hand, since there is no hole in the inspection pattern, it becomes as shown in (S), for example, and the first defect information (Nu ) is obtained, and the final defect information (ru) is obtained by performing an AND operation between the first defect information and the second comparison pattern (ch).

In case Tel, the absence of holes in the inspection pattern is not detected as a defect, and only true defects can be accurately identified.

FIG. 3(d) shows an example of the case (2), that is, a case where there are no holes in both the mask pattern and the inspection pattern. In this case, the same process as described above is performed without generating a pad pattern, and final defect information is obtained.

As mentioned above, by generating or not generating an appropriate pad pattern depending on cases ■ to ■. Appropriate defect detection can be performed regardless of the presence or absence of holes for inserting parts in the master pattern or inspection pattern.

Incidentally, in Cases I and H of the above-mentioned embodiment, a black and white checkered pattern was used as the pad pattern.
Without being limited to this, even if a solid black pattern (the same pattern as the pad pattern of case Ill) is used, the area around 6B[1 can be masked in the same way, but in that case,
The window processing described above becomes unnecessary.

(Effects of the Invention) As described below in detail in 1-1, the present invention has the following advantages. master pattern and
In a pattern defect inspection method in which an inspection pattern on an object to be inspected is compared with binarized information using an imaging means, and a defect in the inspection pattern is determined based on the comparison result,
A portion to be inspected and a non-inspection portion are set according to the inspection pattern, a first comparison pattern for masking the non-inspection portion is formed, and =28 the first comparison pattern and the inspection pattern are compared. The difference information is taken out as first defect information, and a second comparison pattern for setting a defect tolerance area in the first defect information of 0;j is formed based on the first comparison pattern. The first defect information located in an area other than the defect tolerance area may be detected as a defect. In a pattern defect inspection apparatus that compares a master pattern with information obtained by binarizing an inspection pattern on an object to be inspected using an imaging means, and determines defects in the inspection pattern based on the comparison result, a first comparison pattern forming means for setting an inspection target fjlt and a non-inspection portion and forming a first comparison pattern for masking the non-inspection portion; and comparing the first comparison pattern and the inspection pattern. a first defect information generation means for extracting the difference information as first defect information; and a second comparison for setting a defect tolerance area in the first defect information based on the first comparison pattern. Since the second comparison pattern forming means for forming a pattern and the second defect information generating means for detecting the first defect information in an area other than the defect tolerance area as a defect are provided, Not only can small irregularities that do not impair the function of the inspection pattern not be detected, but also only true defects in the inspection pattern can be efficiently detected, regardless of the presence or absence of component insertion holes in the inspection pattern or mask pattern. It has the effect of being able to do it.

[Brief explanation of the drawing]

Figure 1 is a tree! Fig. 2 is a block diagram showing the data processing contents of the pattern defect inspection apparatus shown in Fig. 1, and Fig. 3 shows a typical wiring pattern including holes for inserting parts. A diagram showing a pattern in the second figure number part when detecting an example defect,
Fig. 4 is a diagram showing the principle of window processing, Fig. 5 is a diagram showing the principle of enlargement processing and reduction processing, Fig. 6 is a diagram showing an example of the conventional defect detection method, and Fig. 7 is a diagram showing the principle of It is a figure which shows the pattern in each fat. 1. First central processing unit (CPU), 2 External storage device, 5. Mask pattern generation circuit, 6. Pad pattern generation circuit, 7.. First υ1 other image OR circuit (IE
X-OR circuit), 8... window processing circuit, 9 - mask pattern generation circuit, 10... 1st Q) synchronization delay circuit, 11 CCD camera, 12 sensitivity correction circuit, 13...
・Binarization circuit, 14 Second 1111 Alternative OR circuit (
EX-017 circuit), 15 Second synchronous delay circuit, 16
・Mask circuit.

Claims (2)

[Claims] 1. In a pattern defect inspection method in which a master pattern is compared with information obtained by binarizing an inspection pattern on an object to be inspected using an imaging means, and defects in the inspection pattern are determined based on the comparison results, A portion to be inspected and a non-inspection portion are set, a first comparison pattern for masking the non-inspection portion is formed, the first comparison pattern and the inspection pattern are compared, and the difference information is transmitted to the first comparison pattern. At the same time as extracting defect information, a second comparison pattern is formed for setting a defect tolerance area in the first defect information based on the first comparison pattern; 1. A pattern defect inspection method characterized by detecting defect information of No. 1 as a defect. 2. In a pattern defect inspection apparatus that compares a master pattern with information obtained by binarizing an inspection pattern on an object to be inspected using an imaging means, and determines defects in the inspection pattern based on the comparison result, a first comparison pattern forming means for setting an inspection target portion and a non-inspection portion and forming a first comparison pattern for masking the non-inspection portion; and comparing the first comparison pattern and the inspection pattern. and a second comparison pattern for setting a defect tolerance area in the first defect information based on the first comparison pattern. a second comparison pattern forming means for forming a pattern, and a second defect information generating means for detecting the first defect information in an area other than the defect tolerance area as a defect. Inspection equipment.