JPH0478854A - Wiring pattern inspecting device - Google Patents

Abstract

PURPOSE:To inspect a clearance hole, etc., on an inner layer substrate of a through-hole part of a multi-layered substrate by counting the run length in one-scanning line units after labeling every connection component and detecting the defect based on the summation of the run length. CONSTITUTION:A wiring pattern formed on a substrate 101 is illuminated by a diffusion illuminator 104 and then, a graduation image is formed by an image inputting means 102 provided with a CCD camera, etc. The image is converted to a binary image after comparing with a threshold obtained by a density histogram, etc., by a binarizing means 105 in advance, and labeling processing for assigning different labels to each connection component is performed for the binary image by a labeling means 106. The run length of every connection component is counted in one-scanning line units by a run length counting means 107, and then, the means informs a judging means 112 of the effect. The summation is obtained at every connection component by the means 106 by performing software processing, and then, by comparing it with one or more optional thresholds fixed in advance so as to detect the defect. And in the case of the defect, the means 106 informs the outside of the kind and the coordinate of the defect.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wiring pattern inspection device for inspecting wiring patterns on printed circuit boards, photomasks, etc. for defects.

2. Description of the Related Art Conventionally, inspection for defects in printed circuit boards and the like has relied on human visual inspection. However, as products become smaller and lighter, wiring patterns are becoming more detailed and complex. Under these circumstances, it has become difficult for humans to continue inspecting extremely detailed wiring patterns for long periods of time while maintaining high inspection accuracy, and automation of inspection is strongly desired.

As a defect detection method for wiring patterns, Jorge L., C., Sun and Anil, C.
, 5anz and Anil K, Jain:
'Machine-vision technology
s for 1nspection of print
ed wiring boards and thic
k-filem circuits”, 0pticl
5ociety of America, Vol.
3°No, 9. september, pp145
5-1482, 1986) have introduced a number of methods, which can be roughly divided into two main methods: the design rule method and the comparison method. However, these methods have advantages and disadvantages.

Among them, Jonr, Mandeville (Jonr, Mandeville) is a promising and interesting method.
ovel method for analysis
f printed circuit images”
, IBM J, Res.

DEVELOP,, Vol, 29. No. 1, J
(1985) proposed a method for detecting defects in wiring patterns by shrinking or expanding binarized image data and then thinning the data, which will be described below as a conventional example.

FIG. 6 shows the flow of defect detection processing. (al～(d
i indicates a disconnection detection process, and (e) to (hi) indicate a short circuit detection process.

(al indicates image data including defects, and points b and 0 are considered fatal defects such as abnormal line width and wire breakage, and point a is not considered a defect. As the first step, (bl
Now, image shrinkage processing (processing to remove one pixel from the periphery) is performed. This process causes the defect at point b to become disconnected and exaggerate the defect. fc) as the second step
Then, line thinning processing (repeat the process of removing one pixel from the periphery until the line becomes negative) is performed. As a result, the wiring pattern becomes one line. 3rd step toshiki dl
Now, scan the 3×3 logical mask and create a LUT (look
Defect detection is performed while referring to the up table), and
Points and zero points can be detected as disconnections. Furthermore, the junction points between the terminal portion and the wiring pattern are also detected.

Next, regarding short circuits and line abnormalities, (e) to (hi
This will be explained along the flow of processing.

(e) shows image data including defects, in which point b and point 0 are considered to be fatal defects such as abnormalities between lines and short circuits, and point a is not considered to be a defect.

As the first step (f), the image is expanded (inflated one pixel at a time starting from the surrounding pixels), and this results in b
The points become shorted. In the second step (g), thinning processing is performed to make -1 lines. As the third step (in hl, the 3x3 logical mask is scanned and the LUT
Defects are detected while referring to a look-up table, and shorts can be detected as point b and point 0 are T branches. Furthermore, the junction point between the terminal portion and the wiring pattern is also detected.

In the manner described above, wire breaks, line width abnormalities, short circuits, and line spacing abnormalities can be detected.

Image processing techniques such as thinning, dilation, and contraction are described in detail in Ohmsha, written by Shunji Mori and Toshiko Itakura: @Fundamentals of Image Recognition CI), so a detailed explanation will be omitted. did.

Problems to be Solved by the Invention Now, a method has been described in which a binarized image is contracted or expanded to exaggerate defects, thinned, and a 3×3 logical mask is scanned to detect defects. This method is based on the design rule method and can be said to be a promising method that can reliably detect defects.

However, this method is based on the design rule method and cannot inspect clearance holes in the inner layer substrate of the through-hole portion of a multilayer substrate.

In view of the above-mentioned problems, the present invention provides a wiring pattern inspection device that has a simple configuration and is capable of inspecting clearance holes in an inner layer substrate of a through-hole portion of a multilayer substrate.

Means for Solving the Problems In order to solve the above problems, the technical problems of the present invention are, firstly, an image input means for photoelectrically converting a wiring pattern formed on a printed circuit board, and a grayscale image from the image input means. a binarization means for converting the image into a binary image; a labeling means for assigning a different label to each connected component; a run length counting means for counting the run length in scanning line units for each connected component; A determining means is provided for calculating the sum of the number of pixels counted by the run length counting means for each connected component and comparing the sum with one or more predetermined arbitrary threshold values to detect a defect.

Second, in addition to the first configuration means, the determination means compares the difference between the run length and the run length of the previous line in units of scanning lines for each connected component with a predetermined arbitrary threshold value. be.

Thirdly, in addition to the first and second configuration means, the determination means patterns the difference between the run length and the run length of the previous line for each scanning line for each connected component, and determines the symmetry in the sub-scanning direction. It was designed to do so.

Function The present invention first converts a wiring pattern formed on a printed circuit board into a binary image, performs a labeling process that assigns a different label to each connected component, and labels each connected component in scanning line units. Count run length. The method calculates the sum of the counted run lengths (number of pixels) for each connected component and compares it with one or more predetermined threshold values to detect defects based on area.It is simple and can have multiple arbitrary threshold values set. can.

Second, by comparing the difference between the current run length and the previous run length on a scanning line basis for each connected component with a predetermined arbitrary threshold value, abnormalities such as copper residue in the clearance can be inspected.

Thirdly, by patterning the difference between the current run length and the previous run length in each scanning line for each connected component and evaluating the symmetry in the sub-scanning direction, abnormalities such as copper residue in the clearance are inspected. be able to.

EXAMPLE A first example of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the wiring pattern inspection apparatus of the present invention. In FIG. 1, 101 is a printed circuit board, 102 is an image input means equipped with a diffuse illumination device such as a ring-shaped light guide 104, and an imaging device such as a CCD camera 103, and 105 is a grayscale image converted into a binary image. A binarization means for converting, 106 a labeling means for assigning a different label to each connected component, 107
108 is an I/F for notifying the run length from the run length counting means 107; 112 is the CPU 1o9, memory 110 and I/F 111; The determining means is shown below.

The operation of the above configuration will be explained below.

A wiring pattern formed on a flint board 101 is illuminated with a diffuse illumination device 104 such as a ring-shaped light guide, and the image input means 102 equipped with an imaging device 103 such as a CCD camera (-dimensional or two-dimensional) is used to determine the shading. Get it as an image. In this embodiment, the following description will be made using the image of a rusk scan, and an example will be shown in which a one-dimensional CCD camera is used as an imaging device.

In order to separate the background and the wiring pattern from the grayscale image obtained by the image input means 102, the binarization means 105 compares it with an arbitrary threshold obtained in advance from a density histogram or the like and converts it into a binary image. In this embodiment, in order to limit the inspection to the clearance of the through-hole portion, the background is assumed to be binarized from 11# wiring pattern to 60#. The labeling means 106 performs a labeling process on the binary image obtained by the binarization means 105, assigning a different label to each connected component. The run length counting means 107 inputs the image data labeled by the labeling means 106, counts the run length in units of scanning lines for each connected component,
The determination means 112 is notified via /F108. The determining means 112 includes the CPU 109, memory 110, I/
F 108. 111 constitutes a computer system. In the determination means 106, the run length counting means 107
The run length in scanning line units counted by I/F 108
The total sum is calculated for each connected component by software processing, and defects are detected by comparing them with one or more predetermined threshold values.If it is a defect, the type and coordinates of the defect are
It is notified to the outside via Fill.

By repeating and sequentially performing the above operations, the entire surface of the printed circuit board 101 can be inspected. Also,
This series of operations is performed in synchronization with an appropriate signal such as a line synchronization signal.

Next, the labeling means 106, the run length counting means 107, and the determining means 112 will be explained in more detail.

A detailed block diagram of the labeling means 106 is shown in FIG. 2 and will be described below.

In FIG. 2, 202 is a pixel of interest, 203 is a register indicating an adjacent pixel area of the pixel of interest 202, 205 is a label determination, and 204 is a line memory.

Label determination 205 is performed when the binary image 201 from the binarization means 105 is input and the pixel of interest 202 is "1".

If the 4 pixels in the adjacent pixel area 203 do not have any labels yet, they are given new labels and output to 206, and if the 4 pixels in the adjacent pixel area 203 are labeled, they are given the same labels and output to 206. It is. Interested pixel 2
If 02 is "0#", it is labeled as @O in this embodiment. However, if two or more different types of labels are attached to the adjacent pixel area 203, the oldest label will be removed! :.

It is assumed that a flag 207 is set for both. This is because - In boat fishing, images stored in frame memory are often processed at least twice in order to ensure the sameness of labels, and different labels may be attached to adjacent pixel areas. However, the label is reattached in the second processing. However, this time, we are assuming that processing will be done using the rask scan method, and the label will be flagged in one process, and the subsequent processing will perform the same process by checking this flag and re-labeling. . In addition, this time, the adjacent pixels were removed by 8 connections, but A of the adjacent pixel area 203,
If the C pixel is referred to, there will be 4 connections.

FIG. 3 shows a detailed block diagram of the run length counting means 107, which will be described below.

In FIG. 3, 302 is a comparator, 303 is a threshold value, and 30
6 is a label-time storage register for temporarily storing a label; 3;
07 is a run length counter, and 308 is an XY address counter.

First, the label image 206 is compared with an arbitrary threshold value 303 by the 1 comparator 302 . In this embodiment, since the wiring pattern portion is given a label value of "0", the comparator 302 is configured to detect "0#0#".The output 304 of the comparator 302 is This corresponds to the run length in line units.The run length counter 307 can count the run length by counting the pixel clocks during '1n with the run length signal 304 as an enable signal. The storage register 306 latches the label at the edge of the run/length signal 304 and notifies the judgment means along with the run length count value.Similarly, the XY address counter 308 latches the XY address at the edge of the run length signal 304 and sends it to the judgment means. In addition, in the flag delay circuit, if the flag is set while the run length signal is "1", the determining means 112 is notified.

The determining means 112 includes the CPU 109-memory 110-
A computer system is configured with I/Fs 108 and 111.

FIG. 4 shows a processing phase a of the determining means, and FIG. 5 shows an example of defect detection processing and an example of a calculation table, which will be described below.

The determining means 106 is notified of the run length in units of scanning lines counted by the run length counting means 107 via the I/F 108, and is subjected to software processing according to the processing flow shown in FIG.

As the first step (2), a calculation table as shown in FIG. 5 is created using the run length and XY address (for example, start address) notified via the I/F 108 for each connected component of the label.

In the second step (2), a run length summation calculation is performed for each connected component of the label according to the calculation table. Also, based on the run start address and run length, the average X address in the X direction is determined for each scanning line, and the average of the scanning lines is determined and used as the X address.

Similarly, the average in the Y direction is determined and used as the Y address.

As a third step (2), a comparison is made with one or more predetermined arbitrary threshold values as shown in equation (2).

T tmin≧Total≧'l” tmax(T tmin
: indicates the minimum threshold value of the total sum, T tmax : indicates the maximum threshold value of the total sum) As a result, if it is within the range of the threshold value, it is judged as a good product.

Next, the second embodiment compares the difference between the run length and the run length of the previous line in scanning line units for each connected component with a predetermined arbitrary threshold. explain.

As the first step (2), a calculation table as shown in FIG. 5 is created using the run length and XY address (for example, start address) notified via the I/F 108 for each connected component of the label.

As the second step, at 0, the difference between the run length and the run length of the previous line is calculated for each connected component of the label in accordance with the calculation table for each scanning line.

As a third step (2), a comparison is made with one or more predetermined arbitrary threshold values as shown in equation (2).

Ta2 Difference in run length (Td: Indicates run length difference threshold) Next, in the third embodiment, the difference between the run length and the run length of the previous line is patterned for each connected component in units of scanning lines, and This is for determining symmetry in the scanning direction, and will be explained below using FIG. 4.

As a first step, a calculation table as shown in FIG. 5 is created using the run length and XY address (for example, start address) notified via the I/F 108 for each connected component of the label.

In the second step (2), the difference between the run length and the run length of the previous line is calculated for each scanning line according to the calculation table for each connected component of the label.

As the third step (2), it is determined whether the run length difference pattern is symmetrical in the sub-scanning direction.

Next, an example of defect detection will be described using FIG. 5.

In Figure 5, (a) shows normal clearance, (b
) and (cl indicate defective examples with copper residues 503 and 504, and Tables 1 to 3 below show the values of the calculation tables in correspondence with the scanning lines.

(In the case of normal or clearance of al, the total run length can be expressed as an area if the resolution per pixel of 766 pixels is known. Also, the difference value of the run length is ±2
It is small and symmetrical in the sub-scanning direction.

(bl is an example of a defect with copper residue. It can be seen that the total run length is 700 pixels less, and the run length difference value also lacks symmetry in the sub-scanning direction.

(C) is an example of a defect with copper residue. The total run length is small at 72 pixels, and the difference in run length is large, and symmetry in the sub-scanning direction is also lacking.
Recognize.

(Left below) As explained in detail about the invention, after each connected component is labeled, the run length is counted in scanning line units, and defects are detected based on the sum of the run lengths, that is, the size of the area within the clearance. When processing using the Rask scan method, functions can be efficiently divided into hardware and software. (for example,
To calculate the total number of pixels for each connected component using hardware, the scale of the software is large (and it is difficult to put it into practical use).
Secondly, since the difference from the run length of the previous line is compared with a predetermined arbitrary threshold value, it is possible to easily detect defects such as copper remaining within the clearance.

Furthermore, thirdly, the method of patterning the difference with the run length of the previous line and evaluating the symmetry with respect to the sub-scanning direction is highly effective because it easily reveals the characteristics of defects.

[Brief explanation of drawings]

Fig. 1 is a block wiring diagram of a wiring pattern inspection device according to an embodiment of the present invention, Fig. 2 is a detailed block wiring diagram of a labeling means in the same device, and Fig. 3 is a detailed block wiring diagram of a run length counting means in the same device. , FIG. 4 is a processing flow diagram of the determination means of the same apparatus, FIG. 5 is a diagram showing an example of defect detection, and FIG. 6 is a diagram showing the processing state of the conventional wiring pattern inspection apparatus. 101... Printed circuit board, 102... Image input means, 103... Imaging device, 105... Binarization means, 1
06... Labeling means, 107... Run length counting means, 112... Judgment means, 109... CPU, 11
0...Memory, 501...Clearance, 503.5
04...Copper remaining. Name of agent: Patent attorney Shigetaka Awano and 1 other person No. 4
Figure 5 Figure 6

Claims (3)

[Claims] (1) An image input means for photoelectrically converting a wiring pattern formed on a printed circuit board; and a binarization means for converting a grayscale image from the image input means into a binary image; labeling means for allocating a label for each connected component; run length counting means for counting the run length in scanning line units for each of the connected components; and a run length counting means for calculating the sum of counted pixels from the run length counting means for each connected component. A wiring pattern inspection device comprising: a determining means for detecting a defect by comparing it with one or more predetermined arbitrary threshold values. (2) The wiring pattern inspection according to claim 1, wherein the determining means compares the difference between the run length and the run length of the previous line in units of scanning lines for each connected component with a predetermined arbitrary threshold value. Device. (3) The determining means determines the symmetry in the sub-scanning direction by patterning the difference between the run length and the run length of the previous line in units of scanning lines for each connected component.
, or the wiring pattern inspection device according to claim 2.