JPS62272379A - Wiring pattern inspecting device - Google Patents

Abstract

PURPOSE:To detect a linear disaccord part, which has a narrow width but is long between boundaries, as a defect by expanding and reducing one pattern and using its contour line to detect whether the other pattern has a pattern part and a base material part or not. CONSTITUTION:Illuminating light from an extra-high pressure mercury lamps 3 and 3' is projected to the same positions of a reference printed board 1 and a printed board 1' to be examined through half mirrors 4 and 4'. Reflected light is focused on CCD linear sensors 6 and 6' and passes a binarizing circuit 8, and a binary signal 9 of the reference pattern is inputted to an expanding circuit 10 and a reducing circuit 12. Boundaries of the pattern part are expanded and reduced by one picture element, and an expanded picture signal 11 and a reduced picture signal 13 are inputted to contour line extracting circuits 14 and 16. A coincidence circuit 18 outputs a defect detection signal 19 to a defect indicator 22 if an expanded contour line signal 15 is '1' (contour line part) and a binary signal 9' of the pattern to be examined is '1' (pattern part), and a coincidence circuit 20 outputs a defect detection signal 21 if a reduced contour line signal 17 is '1' and the signal 9' is '0' (base material part).

Description

[Detailed Description of the Invention] i) Detailed Description of the Invention 1' [Industrial Application Field] The present invention relates to an automatic detection device for defects such as chips and protrusions in wiring patterns, and in particular, a device for automatically detecting defects such as chips and protrusions in wiring patterns. The present invention relates to a wiring pattern inspection device suitable for a comparative inspection method in which non-conforming portions at the same location are determined as defects.

[Conventional technology]

The wiring pattern is LSI, printed circuit board.

There are photomasks, etc., but here we will focus on printed circuit boards.

A comparative inspection method is available as a method for detecting defects such as chips and protrusions in wiring patterns of printed circuit boards.

This optically detects the same location on two printed circuit boards with the same wiring pattern, converts the detected image into a video signal using a photoelectric conversion element, binarizes the video signal, and stores it in memory as a two-dimensional pattern. A mismatched portion of each pixel of the two stored wiring patterns is detected as a defect. It is something. A related device for this purpose includes, for example, Japanese Patent Application Laid-Open No. 127574.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when comparing and inspecting the same portion of a printed circuit board pattern serving as a reference and a pattern of a printed circuit board to be inspected, the mismatched portion between the two is a square with a predetermined size outside the pixel. Shape mismatch area P
In this case, a defect is detected only when all pixels do not match.

For such an inspection method, if a reference pattern as shown in Fig. 2 is made up of lines 4 and pads 4 as shown by broken lines, and compared to the pattern to be inspected, there are mismatched areas as shown by diagonal lines. Consider the case where it is detected. The mismatched parts include protruding mismatched parts (al) to ("4)
There are mismatched parts (bl) to (b4) in the shape of % missing. The mismatched protrusions are minute protrusions (al) and wiring thickening (α).
2), large protrusion (A3), elongated protrusion or short circuit (,4
), the chip-shaped mismatched portion is a minute chip (bl), a narrowed wiring (h2), a large chip (h3), a long and narrow chip or a disconnection (h4).

Regarding these defects, in conventional inspection technology, (α3) and (b3) are detected as defects because the reference pattern and the multi-inspection pattern do not match in all pixels of the square-shaped mismatch area P. , other (al) , (A2
), (A4), (bl), (A2),
(b4) is not detected as a defect because the reference pattern and the pattern to be inspected do not match in all pixels in the square-shaped mismatch area P.

However, considering the function of the circuit of the wiring pattern, it is necessary to detect the elongated short circuit (α4) and the elongated wire extension (b4) as defects.

In this way, with conventional technology, it is difficult to detect as defects linear mismatched parts that are long from the wiring pattern boundary but have a small width, such as elongated short circuits (114) and elongated breaks (h4). There is a problem.

An object of the present invention is to detect defects in printed circuit board wiring patterns using a comparative inspection method, and to detect defects if the length of the mismatched portion from the boundary of the wiring pattern is small, and to
It is now possible to inspect as defects protrusions and short circuits where the width of the mismatched part is small but the length from the boundary of the wiring pattern is large, and chips and disconnections where the width of the mismatched part is small but the length from the border of the wiring pattern is large. An object of the present invention is to provide a wiring pattern inspection device.

[Means for solving problems]

The above purpose is to enlarge or reduce one two-dimensional wiring pattern to extract the mismatched part using wiring patterns at the same location of two printed circuit boards, which was conventionally performed by comparison means, This is achieved by extracting the outlines of the reduced wiring patterns and detecting and determining matching portions between the outlines of the enlarged and reduced patterns and the other wiring pattern.

[Effect]

For wiring patterns A and B at the same location on two printed circuit boards obtained from the binary signal, one wiring pattern A is enlarged to the outside of wiring pattern A by the outline extraction circuit of circuit 1, and wiring pattern A is reduced. Circuit 1 The outline extraction circuit creates an enlarged outline pattern A inside the wiring pattern A with a distance of N pixels from the boundary of each pattern part.
l. Create a reduced outline pattern A2.

Next, using the matching circuit, the enlarged contour pattern A1 is used for the wiring pattern B to be inspected, and it is detected whether or not there is a pattern portion of the wiring pattern B on the enlarged contour pattern Al. If there is a patterned portion, that portion is treated as a protruding defect.

Similarly, the wiring pattern El to be inspected is determined by the matching circuit.
ζ, using the reduced outline pattern A2, it is detected whether or not there is a base material part of the wiring pattern B on the reduced outline pattern A2, and if there is a base material part, that part is treated as a chip-like defect. shall be.

By doing this, the protrusion-like mismatched parts whose length from the boundary of wiring pattern B is smaller than N pixels and the chip-like mismatched parts are ignored, and the length from the border is larger than N pixels and the square shape is ignored. This makes it possible to detect defects that cannot be detected in non-conforming areas.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The printed circuit board inspection apparatus shown in FIG. 1 includes an optical system that detects a pattern on a printed circuit board, and a processing circuit that processes a detection signal of the pattern to detect defects. The optical system is a printed circuit board 1. S/, XY tape 2 for scanning the entire printed circuit board 1, 1'. Ultra-high pressure mercury lamp 3.3' to illuminate the pattern.

Half mirrors 4, 4' for changing the optical path of illumination light.

It consists of an imaging lens 5.5' and a CCD linear sensor 6.6' that photoelectrically converts a detected image.

On the other hand, the processing circuit is a binarization circuit 8.8' that binarizes the video signal obtained by the CCD linear sensor 6.6'.

Enlargement circuit 10 for enlarging the two-dimensional pattern formed by the z-valued signal. Similarly, reduction time Ws to reduce the two-dimensional pattern
12. Contour line extraction circuits 14, 16 for extracting contour lines of enlarged patterns and reduced patterns. Matching circuit for detecting patterns on contour lines, 18.20. and a defect indicator n for displaying defect detection results.

The operation of missing number ζ will be explained. First, let's talk about the optical system. Printed circuit board 1. The printed circuit boards 1' are made of the same pattern, and a defect-free reference pattern is used as the printed circuit board 1. A printed circuit board 1' to be a pattern to be inspected is placed on XY tables 2 and 2', respectively. Next, the XY tables 2 and 2' are independently moved and aligned using the alignment marks on both ends of the printed circuit boards so that the same location on both printed circuit boards 1 and 1' can be detected. After the alignment is completed, although not shown in the figure, the XY tables 2.2' are scanned in the same direction and at the same speed by one large XY table on which the XY tables 2, 2' are placed on the same plane.

For illumination, ultra-high pressure mercury lamps 3 and 3' are used, and the illumination light passes through a nozzle mirror and bends the optical path by 90' to a printed circuit board 1°1'.
Irradiate on top. In the printed circuit board 1.1', the pattern portion made of copper has a high reflectance, and the base material portion made of polyimide or the like has a low reflectance. Therefore, in the image formed by reflecting light from the printed circuit board 1.1' onto the COD IJl near sensor 66' using the imaging lenses 5, 5', the pattern part is bright;
The base material part becomes dark. The detected image is the CCD linear sensor 6
．． 6', it is converted into a video signal 7.7'. Video signal 7.
7', the pattern portion is at a high level and the base material portion is at a low level.

Next, the processing circuit will be described. The video signal 7, F' is sampled by a binarization circuit 8.8' based on a synchronization signal synchronized with the drive signal of the CCD linear sensor 6.6', and the base material part is 1 degree and the pattern part is 0 degree in pixel units. It is converted into a series of binary signals -49,9'. Of the converted binary signals 9.9', the standard and pattern binary signals 9 are input to the enlarging circuit 10.

As shown in FIG. 3(,), the enlarged circuit 1O consists of a shift register, a memory, and an OR circuit section.

A shift register is a system in which three rows of memory elements, the same number as the number of synchronizing signals for one scan of the CCD linear sensor 6, are installed in parallel. are sequentially shifted one pixel at a time. The z-valued signal output from the right end of each shift register is input to the memory of that stage and the left end of the shift register of the next stage. The memo IJ 24 stores and reads out a two-dimensional pattern of 3×3 pixels, and sequentially shifts the binarized signal for each pixel from the shift register from left to right in synchronization with the synchronization signal. This allows memory 2
In the four arrays ζ, a two-dimensional pattern detected by the CCD near sensor 6 has a size of 383 pixels and is sequentially stored in accordance with the scanning direction of the CCD near sensor 6. The OR circuit 5 has a 3×3 pixel memory n as shown in FIG.
Take the logical sum of all pixels, and all patterns are 0 (base material part)
O (base material part) is output only when
By outputting 1 (pattern part) when there is a pattern part), the boundary of the pattern part of the two-dimensional pattern is expanded pixel by pixel. In this way, the enlargement circuit 10 enlarges the pattern portion to 1. An enlarged image signal 11 whose base material portion is O is output.

By the way, the binarized signal 9 is connected in parallel with the expansion circuit 10,
The signal is input to the reduction circuit 11. As shown in FIG. 3(b) &
It consists of four AND circuits. The shift register 26 is the same as the memory n of the enlargement circuit 10, and the memo IJ 27 contains the memory 24 of the enlargement circuit IO (l!-Similarly, the CCD IJI near sensor 6 detects the two-dimensional pattern is a large scale of 3x3 pixels and C
The data are sequentially stored in accordance with the scanning direction of the OD IJ near sensor 6. The AND circuit device is shown in Figure 3(b). It calculates the AND of all the pixels of Memo II 27 of 3 x 3 pixels, and only when the whole pattern becomes 1 (pattern part), it becomes 1 (
By outputting O (base material part) when there is even one 0 (pattern part), the boundary of the pattern part of the two-dimensional pattern is reduced pixel by pixel.

In this way, the pattern portion is reduced to 1 by the reduced image 1812.
, a reduced image signal 13 whose base material portion is O is output.

Expansion circuit 10 just mentioned. The reduction circuit 12 performs a process of enlarging or reducing the boundaries of pattern portions of a 12-dimensional pattern one pixel at a time. Therefore, when enlarging or reducing N pixels (N>t), the enlarging circuit and reducing circuit just described are connected in N stages, and the output of the final stage is used as the enlarged image signal 11. It is assumed that the reduced image signal 13 is used.

Enlargement circuit 10. The enlarged image signal 11 outputted from the reduction circuit 12. The reduced image signal 13 is sent to the contour extraction circuit 14゜16.
is input. The contour extraction circuits 14 and 16 are the same, and as shown in FIG.
30. It consists of a NAND circuit 31 and an AND circuit 32. Shift register 4, memory 30 is the enlarged image M10's shift register n, memory 24. Shift register 26 of reduction circuit 12. It is the same as the memory 27. The NAND circuit 31 is for negating the AND of four cross-shaped pixels of the memory (9), and even one of the four pixels is 0 (base material part).
When there is, it outputs 1, and when all four pixels are in the pattern part, it outputs 0. The AND gate j832 is for taking the AND of the center pixel of the memory (9) and the NAND circuit 31.
1 is output only when the center pixel is 1 (pattern part) and at least one of the four surrounding cross-shaped pixels is O (base material part).

As a result, the boundary of the pattern portion of the two-dimensional pattern is extracted pixel by pixel, and the enlarged contour signal 15. A reduced contour signal 17 is output.

By the way, the enlargement port wA10. Since the reduction circuit 121 and the contour extraction circuit 14.16 perform processing using surrounding pixels on the upper, lower, left, and right sides of the target pixel, the output of the first and last pixel of each scanning line is meaningless as pattern information. Expansion circuit 10
．． If the number of stages of the reduction circuit 12 is N, information of //+1 pixel is lost, so it is necessary to enlarge the detection area in advance.

The enlarged contour signal 15 is input to the matching circuit 18, and the reduced contour signal 17 is input to the matching circuit. As shown in FIG. 5(α), the coincidence circuit 18 is composed of an AND circuit, and receives the enlarged contour signal 15 and the binary signal 9' of the pattern to be inspected. At this time, the binary signal 9/ is inputted in synchronization with the enlarged contour signal 15 so that the pattern to be inspected is a signal that detects the same portion of the reference pattern. The AND circuit outputs the defect detection signal 19 as 1 only when the enlarged contour signal 15 is 1 (outline portion) and the binarized signal 9' is 1 (pattern portion). Thereby, when a pattern portion of the pattern to be inspected is located on the enlarged contour line of the reference pattern, it is detected as a defective portion.

On the other hand, the matching circuit 20 is composed of an AND circuit as shown in FIG. , the binary signal 9' is input in synchronization with the reduced contour signal 17 so that it is a detection signal for the same location on the printed circuit board.The AND circuit is inputted when the reduced contour signal 17 is 1
(outline portion), only when the binary signal 9' is O (substrate portion), it is determined that there is a defect and the defect detection signal 21 is set to 1 and output. Thereby, when the base material portion of the pattern to be inspected is on the reduced contour line of the reference pattern, it is detected as a defective portion.

Next, the size of the defect detected in FIG. 6 will be described. When the binary signal 9' of the double inspection pattern is expressed in two dimensions, it becomes a binary pattern (pattern part A, base material part 36)
becomes. Similarly, the contour line extraction circuit 14. 16 is the enlarged contour signal 15. When the reduced contour signal 17 is expressed in two dimensions and superimposed on the previously expressed z-valued pattern, enlarged contour patterns 41, 43, . This results in reduced contour patterns 42 and 44.

(α) is N1 pixel enlarged and reduced enlarged contour pattern 4
1° reduced contour pattern 42. (b) is N1 pixel (N
t > Nt) Expanded and contracted enlarged contour pattern 4
3. This is a reduced outline pattern (■).

As shown in FIG. 6(α), when enlarged and reduced by N1 pixels, the enlarged contour pattern 42 and the pattern part of the binarized pattern match at 38, and the protrusion 37° is like a protrusion. The defects, and the base material parts of the reduced outline pattern 42 and the binarized pattern match at portions 39 and 40, and the portions 39 and 40 are determined to be chip-like defects, respectively. Similarly, when N8 pixels are enlarged or reduced as shown in FIG. 6(A), only the protrusion 37 is determined to be a protrusion-like defect, and only the chipped portion 40 is determined to be a chipped defect.

In this way, the expansion circuit 10. By changing the number N of pixels for enlargement and reduction in the reduction circuit 12, it is possible to change the size of the defect to be detected.

The detected defect is input to the defect display 22 as a defect detection signal 19.21, and the defect signal is stored and displayed as coordinates.

By the way, the explanation has been made assuming that the printed circuit board of the i-pattern to be tested is 1' and the printed circuit board of the reference pattern is 1, but if this is installed in reverse, Pattern part 35 of binarization pattern
If so, that portion can be detected as a chip-like defect, and when the base material portion 36 of the binarized pattern is present on the reduced outline pattern 42, that portion can be detected as a protrusion-like defect.

However, if the defect is elongated and has a large length from the boundary of the pattern portion but a small width, it cannot be detected as a defect because the defect disappears by the enlarging/reducing process. Therefore, as mentioned above, it is desirable to always set the reference pattern on the 1 side.

〔Effect of the invention〕

As explained above, according to the present invention, one pattern is enlarged or reduced to obtain its outline, and this is used to detect the presence or absence of a pattern part or a base material part of the other pattern, thereby forming a pattern. Defects can be detected. Therefore, mismatched portions with small dimensions from the wiring pattern boundary, such as thick or thin lines, minute protrusions, and chips, are not detected as defects. Further, there is an effect that a linear mismatched portion having a small length from the boundary but a long length from the boundary, which cannot be detected by conventional inspection methods, can be detected as a defect.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a printed circuit board inspection apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of types of defects, and FIG. 3 is a configuration diagram of an enlarged circuit and a reduced circuit of the printed circuit board inspection apparatus according to an embodiment. Fig. 4 is a block diagram of the outline extraction circuit of the printed circuit board inspection device of the embodiment, Fig. 5 is a block diagram of the matching circuit of the printed circuit board inspection device of the embodiment, and Fig. 6 is an explanatory diagram of the size of detected defects. . 1, 1'...Printed circuit board 2.2'...xY
Table 3.3'...Ultra high pressure mercury lamp 4.4'.
...Half mirror 5, 5'...To imaging lens 6'...CCD linear sensor 48'...Binarization circuit 10...Enlargement circuit 1
2... Reduction circuit 1416... Outline extraction circuit 1a20...-number circuit 22... To defect indicator 2a 29... Shift register 2427, 30... Memory 6... OR circuit 2e 1λ M...
ε kiln 1. ,, /E

Claims (1)

[Claims] 1. A plurality of optical systems that obtain real images of wiring patterns at two same locations, a plurality of imaging devices that convert the optical real images obtained by each of the optical systems into video signals, and a plurality of imaging devices that convert the real images obtained by each of the optical systems into video signals; a plurality of binarization circuits that binarize the video signals;
In a wiring pattern inspection device having comparison means for detecting defects by comparing the signals obtained by the respective binarization circuits, one of the patterns is enlarged and reduced, the outlines of each are extracted, and the enlarged and determining means for determining a defect when there is a pattern part of the other wiring pattern on the reduced outline pattern and when there is a difference part of the other wiring pattern on the reduced outline pattern. Characteristic wiring pattern inspection equipment.