JPH02142180A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease a wiring delay time by using a long wiring without impairing the performance of a basic gate and layout property by arranging low-current gate cells and high-current gate cells on a gate array substrate, and using the high-current gates when the long wiring is formed. CONSTITUTION:Many gate cells are arranged on a gate part 14 of a chip 11 in a matrix pattern. Cells 15 indicated by shaded parts are high-current gate cells exclusive for long wirings. Other cells 16 are low-current gate cells. The high-current gate 15 has a constitution wherein a current flowing through a switching transistor and an emitter follower transistor is twice a current flowing through a transistor for the low-current gate. Therefore, when the high-current gate is used when the wiring is long, a wiring delay time can be made quicker than the time when the low current cell is used. Thus, the wiring delay time can be decreased by using the high-current gate 15 when a long wiring 17 is formed. For a wiring 18 with a short distance between the gates, the low-current gates 16 are used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type semiconductor integrated circuit, and particularly to the basic gate cell structure thereof.

[Conventional technology]

Conventionally, this type of gate array type semiconductor integrated circuit,
Basic cells forming one type of AND/NAND basic gate were arranged in an array.

[Problem to be solved by the invention]

In the conventional gate array type semiconductor integrated circuit described above, a current adjustment element is disposed within the basic gate in order to speed up the wiring delay time. That is, when wiring is long, a current adjustment element placed in the basic gate is used to increase the current driving the gate, thereby speeding up the wiring delay time.

When the wiring was short, the gate was constructed without using a current adjustment element placed inside the gate. As described above, since an extra element for current adjustment must be placed in the basic gate, there is a disadvantage that the layout of the basic gate becomes poor and the element usage rate also decreases.

[Means to solve the problem]

The gate array type semiconductor integrated circuit of the present invention has a plurality of low current gate cells and a plurality of high current gate cells at fixed positions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 3A is a circuit diagram of a two-way AND/NAND low current gate cell of a bipolar gate array using a CML circuit. Inside the basic cell, three switching transistors 301 to 303, emitter follower transistors 305, 306, constant current source transistor 304, collector resistor 311, 312, emitter resistor 313, and emitter follower resistor 314, 315 are arranged. are doing.

FIG. 3B is a circuit diagram of a high current gate cell in which the drive current is twice that of the low current gate cell. In the basic cell of the high current gate, there are transistors 321 to 323 of emitter size that can flow twice the current of the low current gate, transistors 326 to 329 for emitter followers each having twice the number of the basic gate, and transistors 326 to 329 for a constant current source. transistors 324, 32
5. Collector resistance 331-334, emitter resistance 335
336, emitter follower resistors 337 to 340 are arranged, and the gate is driven with twice the current.

FIG. 1 is a plan view of an embodiment of the present invention.

A large number of gate cells are arranged in a matrix in the gate section 14 of the chip 11, and the hatched cell 15 is a high current gate cell dedicated to long wiring;
6 is a low current gate cell.

As shown in FIG. 3B, the high current gate 15 has a configuration in which the current flowing through the switching transistor and emitter follower transistor is twice the current flowing through the low current gate transistor in FIG. 3A. , if a high current gate is used when the wiring is long, the wiring delay time will be faster than if a low current gate cell is used. Therefore, as shown in the figure, when a long wiring 17 is formed, the wiring delay time can be reduced by using the high current gate 15. Furthermore, in the case of a short wiring 18 between gates, a low current gate 16 is used.

In FIG. 1, 12 indicates an input/output circuit section, and 13 indicates a peripheral circuit section.

FIG. 2 is a plan view of another embodiment of the invention.

In order to output the necessary signals generated by the gate section 24 of the chip 21 to the outside of the chip 21, an output buffer 27 provided around the inside of the chip is used, but the wiring from the gate section 24 to the output buffer 27 is 28 is longer than the inter-gate wiring in the gate portion 24, and the wiring delay time becomes worse. Therefore, a high current gate cell 25 dedicated to long wiring is arranged along the outer periphery of the gate portion 24. Gate part 2
4 to the output buffer 27, there is an advantage that the high current gate 25 is used to reduce the wiring delay time of a long wiring. Inside the high current gate cell group 25, a large number of low current gate cells 26 are arranged in a matrix.

〔Effect of the invention〕

As explained above, the present invention arranges low-current gate cells and high-current gate cells on the base of the gate array, and uses high-current gates when long wiring occurs, thereby impairing the performance and layout of the basic gate. This has the effect of reducing wiring delay time for long wiring without causing problems.

Circuit diagram of a current gate. FIG. 3B is a circuit diagram of a high current gate.

11.21... Chip, 12.22...
Input/output circuit section, 13.23... Peripheral circuit section such as constant voltage generation circuit, 14.24... Gate section in which low current gate cells and high current gate cells are arranged, 15.25.
...High current gate cell, 16.26...Low current gate cell, 17...Long inter-gate wiring, 27
...Output buffer in the input/output circuit, 28...
...Wiring between gate section and output buffer, 18...
...Short inter-gate wiring, 31...Input terminal, 32
...Reference power supply terminal, 33...
Reference voltage supply terminal, 34...Output terminal, 35.
...Output terminal, 36...High-side power supply, 3
7...Low side power supply.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

Fig. 1 is a plan view of one embodiment of the present invention, Fig. 2 is a plan view of another embodiment of the invention, and Fig. 3 A is a low 1B paddle diagram.

Claims (1)

[Claims] A gate array type semiconductor integrated circuit characterized in that a plurality of low current gate cells and a plurality of high current gate cells are formed in a predetermined arrangement.