JPH02140967A - 自動レイアウト装置 - Google Patents

自動レイアウト装置

Info

Publication number
JPH02140967A
JPH02140967A JP63295025A JP29502588A JPH02140967A JP H02140967 A JPH02140967 A JP H02140967A JP 63295025 A JP63295025 A JP 63295025A JP 29502588 A JP29502588 A JP 29502588A JP H02140967 A JPH02140967 A JP H02140967A
Authority
JP
Japan
Prior art keywords
chip
limit
automatic layout
assembling
automatically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63295025A
Other languages
English (en)
Inventor
Yoshiaki Daimon
義明 大門
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63295025A priority Critical patent/JPH02140967A/ja
Publication of JPH02140967A publication Critical patent/JPH02140967A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自動レイアウト装置に関し、特に組立基準を考
慮に入れた装置に関する。
〔従来の技術〕
従来の自動レイアウト装置はパッド位置及びチップサイ
ズの設定を自動レイアウトと共に行ってしまうか、ある
いは最初にパッド位置及びチップサイズの制限を設定し
てから自動レイアウトを行うかであった。
〔発明が解決しようとする課題〕
上述した従来のパッド位置及びチップサイズの設定を自
動レイアウトと共に行う装置では、自動レイアウトを行
った後で、組立基準にあわない場合、もう−度やりなお
さなければならないという欠点があり、パッド位置、チ
ップサイズを最初に設定してから自動レイアウトを行う
装置では完全な自動レイアウトを行うことができず、前
もって、組立基準よりパッド位置、チップサイズの制限
を決めなくてはいけないという欠点がある。
〔課題を解決するための手段〕
本発明の自動レイアウト装置は、ＩＣの組立図と組立基
準よりパッド位置、チップサイズの制限を計算する手段
と、その制限にもとづいて自動レイアウトを行っている
。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明のブロックダイヤグラムであり、また、
第２図はＩＣの組立図である。まずＩＣの組立図（リー
ドフレーム）よりアイランドとチップまでの距離を０．
２〜０．７Ｂとして、アイランドに搭載可能なチップサ
イズの制限を設定する。次に、パッドとインナーリード
との距離が１ｍｍ〜２閣になるような制限と、パッドと
インナーリードな結んだポンディングワイヤーの間隔が
１８０μｍ以上になるような制限と、ポンディングワイ
ヤーとインナーリードの接着部分が０．２〜０．３皿に
なるような制限よりパッド位置の制限を設定する。以上
の組立基準と従来の自動レイアウトに利用された設計基
準よりチップレベルの自動レイア
【図面の簡単な説明】
第１図は本発明のブロックダイヤグラム、第２図はＩＣ
の組立図である。 １・・・・・・アイランド、２・・・・・・チップ、３
・・・・・・インナーリード、４・・・・・・ポンディ
ングパッド、５・・・・・・ポンディングワイヤー　６
・・・・・・アイランドとチップの間の距離、７・・・
・・・パッドとインナーリードの間の距離、８・・・・
・・ポンディングワイヤーの間隔、９・・・・・・ポン
ディングワイヤーとインナーリードの接着部分。 代理人　弁理士　　内　原　　　音 風上説明したように本発明はＩＣの組立図と組立基準よ
りパッド位置、チップサイズの制限を考慮に入れて自動
レイアウトすることにより、組立可能なチップをＩＣの
組立図と回路図よりチップレベルで自動レイアウトがで
きる効果がある。 茶Ｚ図

Claims (1)

    【特許請求の範囲】
  1. ＩＣの組立図面をＥＷＳ上に入力する装置を有し、その
    組立図と、入力した組立基準より、ＩＣのパッド位置及
    びチップサイズの制限を計算する装置を有し、かつその
    制限より、パッドを含めて、チップレベルで自動レイア
    ウトを行うことを特徴とする自動レイアウト装置。
JP63295025A 1988-11-21 1988-11-21 自動レイアウト装置 Pending JPH02140967A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63295025A JPH02140967A (ja) 1988-11-21 1988-11-21 自動レイアウト装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63295025A JPH02140967A (ja) 1988-11-21 1988-11-21 自動レイアウト装置

Publications (1)

Publication Number Publication Date
JPH02140967A true JPH02140967A (ja) 1990-05-30

Family

ID=17815354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63295025A Pending JPH02140967A (ja) 1988-11-21 1988-11-21 自動レイアウト装置

Country Status (1)

Country Link
JP (1) JPH02140967A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04236668A (ja) * 1991-01-21 1992-08-25 Nec Corp Ｌｓｉチップ設計システム
JPH04236669A (ja) * 1991-01-21 1992-08-25 Nec Corp Ｉｃペレットサイズ計算装置および方法
WO1999059090A1 (en) * 1998-05-13 1999-11-18 Seiko Epson Corporation Method and apparatus for determining wiring route on circuit board and information storage medium

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04236668A (ja) * 1991-01-21 1992-08-25 Nec Corp Ｌｓｉチップ設計システム
JPH04236669A (ja) * 1991-01-21 1992-08-25 Nec Corp Ｉｃペレットサイズ計算装置および方法
WO1999059090A1 (en) * 1998-05-13 1999-11-18 Seiko Epson Corporation Method and apparatus for determining wiring route on circuit board and information storage medium
US6397376B1 (en) 1998-05-13 2002-05-28 Seiko Epson Corporation Method and apparatus for determining wiring route in circuit board and information storage medium

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