JPH0213729U - - Google Patents
Info
- Publication number
- JPH0213729U JPH0213729U JP9265488U JP9265488U JPH0213729U JP H0213729 U JPH0213729 U JP H0213729U JP 9265488 U JP9265488 U JP 9265488U JP 9265488 U JP9265488 U JP 9265488U JP H0213729 U JPH0213729 U JP H0213729U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor element
- electrodes
- terminals
- thin metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の半導体装置の断面図、第２図
は従来の半導体装置の断面図である。
１…半導体素子、２ａ…リードフレームのリー
ド部、２ｂ…リードフレームの素子搭載部、３…
金属細線、４…モールド樹脂。
FIG. 1 is a sectional view of a semiconductor device of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2a... Lead part of lead frame, 2b... Element mounting part of lead frame, 3...
Fine metal wire, 4...Mold resin.
Claims (1)
記半導体素子の電極と前記リードフレームの端子
とを金属細線により結線し更に樹脂によりモール
ド成形して成る半導体装置において、半導体素子
の電極とリードフレームの端子とを結ぶ金属細線
の中央部に１巻以上のらせん状ループを設けた事
を特徴とする半導体装置。 In a semiconductor device in which a semiconductor element is mounted on a lead frame, and the electrodes of the semiconductor element and the terminals of the lead frame are connected with thin metal wires and then molded with resin, the electrodes of the semiconductor element and the terminals of the lead frame are connected. A semiconductor device characterized in that a spiral loop of one or more turns is provided in the center of a thin metal wire connecting the two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9265488U JPH0213729U (en) | 1988-07-12 | 1988-07-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9265488U JPH0213729U (en) | 1988-07-12 | 1988-07-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0213729U true JPH0213729U (en) | 1990-01-29 |
Family
ID=31317091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9265488U Pending JPH0213729U (en) | 1988-07-12 | 1988-07-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0213729U (en) |
-
1988
- 1988-07-12 JP JP9265488U patent/JPH0213729U/ja active Pending