JPH0351850U - - Google Patents

Info

Publication number
JPH0351850U
JPH0351850U JP11217489U JP11217489U JPH0351850U JP H0351850 U JPH0351850 U JP H0351850U JP 11217489 U JP11217489 U JP 11217489U JP 11217489 U JP11217489 U JP 11217489U JP H0351850 U JPH0351850 U JP H0351850U
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
package
tip
processed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11217489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11217489U priority Critical patent/JPH0351850U/ja
Publication of JPH0351850U publication Critical patent/JPH0351850U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案実施例による半導体装置の斜視
外形図、第2図は実装組立図、第3図、第4図は
第1図の応用実施例の側面図、第5図は従来の半
導体装置の実装組立図である。図において、 1……半導体素子、2……外部リード、2a…
…先端部、2b……湾曲成形部、3……パツケー
ジ。
Fig. 1 is a perspective external view of a semiconductor device according to an embodiment of the present invention, Fig. 2 is a mounting assembly diagram, Figs. 3 and 4 are side views of an applied embodiment of Fig. 1, and Fig. 5 is a conventional semiconductor device. FIG. 3 is an assembly diagram of the device. In the figure, 1...semiconductor element, 2...external lead, 2a...
...Tip part, 2b...Curved molded part, 3...Package.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パツケージより引出した外部リードを細線に加
工した上で、その先端部との間の中間部位をカー
ル状に湾曲成形したことを特徴とする半導体装置
A semiconductor device characterized in that an external lead pulled out from a package is processed into a thin wire, and an intermediate portion between the lead and the tip thereof is formed into a curled shape.
JP11217489U 1989-09-26 1989-09-26 Pending JPH0351850U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11217489U JPH0351850U (en) 1989-09-26 1989-09-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11217489U JPH0351850U (en) 1989-09-26 1989-09-26

Publications (1)

Publication Number Publication Date
JPH0351850U true JPH0351850U (en) 1991-05-20

Family

ID=31660623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11217489U Pending JPH0351850U (en) 1989-09-26 1989-09-26

Country Status (1)

Country Link
JP (1) JPH0351850U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003024200A (en) * 2001-07-17 2003-01-28 Ado:Kk Decorative bedding
JP2009119194A (en) * 2007-11-19 2009-06-04 Hinomoto Shingu Kk Bag body and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003024200A (en) * 2001-07-17 2003-01-28 Ado:Kk Decorative bedding
JP2009119194A (en) * 2007-11-19 2009-06-04 Hinomoto Shingu Kk Bag body and its manufacturing method

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