JPH02136331U - - Google Patents

Info

Publication number
JPH02136331U
JPH02136331U JP1989044755U JP4475589U JPH02136331U JP H02136331 U JPH02136331 U JP H02136331U JP 1989044755 U JP1989044755 U JP 1989044755U JP 4475589 U JP4475589 U JP 4475589U JP H02136331 U JPH02136331 U JP H02136331U
Authority
JP
Japan
Prior art keywords
metal substrate
resin
protrusion
semiconductor device
boundary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989044755U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989044755U priority Critical patent/JPH02136331U/ja
Publication of JPH02136331U publication Critical patent/JPH02136331U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａ，ｂ，ｃは夫々本考案を説明する為の
裏面図、側面図、およびＡＡ線断面図、第２図と
第３図は本考案を説明する為の断面図、第４図は
従来例を説明する為の裏面図である。 Figures 1a, b, and c are respectively a back view, a side view, and a sectional view taken along line AA to explain the present invention. Figures 2 and 3 are sectional views to explain the present invention. Figure 4 is a back view for explaining a conventional example.

Claims (1)

【実用新案登録請求の範囲】 (1) 金属基板の主面に半導体チツプを固着し、
裏面が樹脂と同一平面を成して露出するように樹
脂封止した半導体装置において、 前記同一平面を成す金属基板と樹脂との境界付
近の前記金属基板表面に、前記金属基板と樹脂と
の境界に沿つてバリ止め用の突起を設けたことを
特徴とする半導体装置。 (2) 前記突起は、前記金属基板の溝加工を処し
その結果前記溝の周囲に盛り上がつた金属基板材
料であることを特徴とする請求項第１項に記載の
半導体装置。 (3) 前記突起は、モールド工程において金型表
面に当接し、圧力が加えられることにより前記金
型表面と密接するように変形したものであること
を特徴とする請求項第１項に記載の半導体装置。[Scope of claims for utility model registration] (1) A semiconductor chip is fixed to the main surface of a metal substrate,
In a semiconductor device resin-sealed so that the back surface is exposed on the same plane as the resin, a boundary between the metal substrate and the resin is formed on the surface of the metal substrate near the boundary between the metal substrate and the resin, which form the same plane. A semiconductor device characterized in that a protrusion for preventing burrs is provided along the . (2) The semiconductor device according to claim 1, wherein the protrusion is a metal substrate material that is raised around the groove as a result of processing a groove in the metal substrate. (3) The protrusion is deformed to come into close contact with the mold surface by contacting the mold surface during the molding process and applying pressure. Semiconductor equipment.
JP1989044755U 1989-04-17 1989-04-17 Pending JPH02136331U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989044755U JPH02136331U (en) 1989-04-17 1989-04-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989044755U JPH02136331U (en) 1989-04-17 1989-04-17

Publications (1)

Publication Number Publication Date
JPH02136331U true JPH02136331U (en) 1990-11-14

Family

ID=31558333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989044755U Pending JPH02136331U (en) 1989-04-17 1989-04-17

Country Status (1)

Country Link
JP (1) JPH02136331U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714943A (en) * 1993-06-18 1995-01-17 Matsushita Electric Works Ltd Chip carrier
JP2018029183A (en) * 2013-04-17 2018-02-22 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ Optoelectronic component and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4832616U (en) * 1971-08-21 1973-04-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4832616U (en) * 1971-08-21 1973-04-20

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714943A (en) * 1993-06-18 1995-01-17 Matsushita Electric Works Ltd Chip carrier
JP2018029183A (en) * 2013-04-17 2018-02-22 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ Optoelectronic component and method for manufacturing the same

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