JPS63193854U - - Google Patents

Info

Publication number
JPS63193854U
JPS63193854U JP8432487U JP8432487U JPS63193854U JP S63193854 U JPS63193854 U JP S63193854U JP 8432487 U JP8432487 U JP 8432487U JP 8432487 U JP8432487 U JP 8432487U JP S63193854 U JPS63193854 U JP S63193854U
Authority
JP
Japan
Prior art keywords
molded
region
lead frame
area
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8432487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8432487U priority Critical patent/JPS63193854U/ja
Publication of JPS63193854U publication Critical patent/JPS63193854U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るリードフレームの概略断
面図、第2図は同概略平面図、第3図は被膜の剥
離状態を示す断面図、第4図は従来例を示す断面
図である。 A……リードフレーム、1……ダイパツト、2
……モールド部、5……樹脂被膜、6……境界線
、7……モールド領域、8……非モールド領域。
FIG. 1 is a schematic sectional view of a lead frame according to the present invention, FIG. 2 is a schematic plan view thereof, FIG. 3 is a sectional view showing a peeled state of the film, and FIG. 4 is a sectional view showing a conventional example. A...Lead frame, 1...Die part, 2
...Mold part, 5...Resin coating, 6...Boundary line, 7...Mold area, 8...Non-mold area.

Claims (1)

【実用新案登録請求の範囲】 半導体素子が固設され、且つ表面にモールド部
が形成されるモールド領域と、モールド部が形成
されない非モールド領域とを有すると共に、半導
体装置の基板として用いられるリードフレームに
おいて、 少なくともモールド領域と非モールド領域との
境界線から非モールド領域に亘つて、バリ剥離用
の被膜を形成したことを特徴とするリードフレー
ム。
[Claims for Utility Model Registration] A lead frame that has a molded area on which a semiconductor element is fixed, a molded part is formed on the surface, and a non-molded area where no molded part is formed, and is used as a substrate of a semiconductor device. A lead frame characterized in that a film for removing burrs is formed at least from the boundary line between the molded region and the non-molded region to the non-molded region.
JP8432487U 1987-05-29 1987-05-29 Pending JPS63193854U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8432487U JPS63193854U (en) 1987-05-29 1987-05-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8432487U JPS63193854U (en) 1987-05-29 1987-05-29

Publications (1)

Publication Number Publication Date
JPS63193854U true JPS63193854U (en) 1988-12-14

Family

ID=30938723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8432487U Pending JPS63193854U (en) 1987-05-29 1987-05-29

Country Status (1)

Country Link
JP (1) JPS63193854U (en)

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