JPS6395247U - - Google Patents
Info
- Publication number
- JPS6395247U JPS6395247U JP19133086U JP19133086U JPS6395247U JP S6395247 U JPS6395247 U JP S6395247U JP 19133086 U JP19133086 U JP 19133086U JP 19133086 U JP19133086 U JP 19133086U JP S6395247 U JPS6395247 U JP S6395247U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- groove
- substrate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図、第２図はこの考案の一実施例を示す断
面図と斜視図、第３図、第４図は樹脂の封止工程
を説明するための断面図、第５図は従来の半導体
装置用基板を示す断面図である。
図中、１は半導体装置用基板、２は半導体チツ
プ、３はワイヤ、４は封止用樹脂、５は溝である
。尚、図中同一符号は同一又は相当部分を示す。
Figures 1 and 2 are a sectional view and a perspective view showing one embodiment of this invention, Figures 3 and 4 are sectional views for explaining the resin sealing process, and Figure 5 is a conventional semiconductor. FIG. 2 is a cross-sectional view showing a device substrate. In the figure, 1 is a semiconductor device substrate, 2 is a semiconductor chip, 3 is a wire, 4 is a sealing resin, and 5 is a groove. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ツプをダイボンドして後ワイヤボンドを施し、次
に半導体チツプおよびワイヤ上に保護のための樹
脂を塗布するものにおいて、上記半導体基板上の
半導体チツプがダイボンドされる外周に溝を設け
たことを特徴とする半導体装置用基板。 (2) 溝の断面形状をＶ字形とした実用新案登録
請求の範囲第１項記載の半導体装置用基板。 (3) 溝の断面形状をＵ字形とした実用新案登録
請求の範囲第１項記載の半導体装置用基板。[Claims for Utility Model Registration] (1) In a device in which a semiconductor chip is die-bonded to a predetermined position on a semiconductor device substrate, wire bonding is performed after that, and then a protective resin is applied on the semiconductor chip and the wire. . A substrate for a semiconductor device, characterized in that a groove is provided on the outer periphery of the semiconductor substrate to which a semiconductor chip is die-bonded. (2) A semiconductor device substrate according to claim 1, wherein the groove has a V-shaped cross-section. (3) The semiconductor device substrate according to claim 1, wherein the groove has a U-shaped cross-section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19133086U JPS6395247U (en) | 1986-12-11 | 1986-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19133086U JPS6395247U (en) | 1986-12-11 | 1986-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6395247U true JPS6395247U (en) | 1988-06-20 |
Family
ID=31145371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19133086U Pending JPS6395247U (en) | 1986-12-11 | 1986-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6395247U (en) |
-
1986
- 1986-12-11 JP JP19133086U patent/JPS6395247U/ja active Pending