JPH0213338B2 - - Google Patents

Info

Publication number
JPH0213338B2
JPH0213338B2 JP56180579A JP18057981A JPH0213338B2 JP H0213338 B2 JPH0213338 B2 JP H0213338B2 JP 56180579 A JP56180579 A JP 56180579A JP 18057981 A JP18057981 A JP 18057981A JP H0213338 B2 JPH0213338 B2 JP H0213338B2
Authority
JP
Japan
Prior art keywords
terminal device
buffer memory
data
terminal
output data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56180579A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5882331A (ja
Inventor
Hideaki Genma
Masashi Hino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56180579A priority Critical patent/JPS5882331A/ja
Publication of JPS5882331A publication Critical patent/JPS5882331A/ja
Publication of JPH0213338B2 publication Critical patent/JPH0213338B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
JP56180579A 1981-11-11 1981-11-11 端末制御方式 Granted JPS5882331A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56180579A JPS5882331A (ja) 1981-11-11 1981-11-11 端末制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56180579A JPS5882331A (ja) 1981-11-11 1981-11-11 端末制御方式

Publications (2)

Publication Number Publication Date
JPS5882331A JPS5882331A (ja) 1983-05-17
JPH0213338B2 true JPH0213338B2 (enrdf_load_html_response) 1990-04-04

Family

ID=16085727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56180579A Granted JPS5882331A (ja) 1981-11-11 1981-11-11 端末制御方式

Country Status (1)

Country Link
JP (1) JPS5882331A (enrdf_load_html_response)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022775B2 (ja) * 1977-05-11 1985-06-04 株式会社日立製作所 入出力システム
JPS55143635A (en) * 1979-04-24 1980-11-10 Nec Corp Input-output controller

Also Published As

Publication number Publication date
JPS5882331A (ja) 1983-05-17

Similar Documents

Publication Publication Date Title
JPH08197788A (ja) プリンタ制御装置の画像データ読出し回路
JPH0776932B2 (ja) デ−タ伝送方式
JP2766216B2 (ja) 情報処理装置
JPH0213338B2 (enrdf_load_html_response)
JPS59188731A (ja) 情報処理方式
JPS59200362A (ja) 端末装置の制御方式
JPH0522307A (ja) データ送信装置
JP2735112B2 (ja) 数値制御装置のデータ・リード・ライト方式
JPH0115900B2 (enrdf_load_html_response)
JP2876576B2 (ja) 数値制御装置
JPH0426476B2 (enrdf_load_html_response)
JPS61206047A (ja) コンピユ−タのバツクアツプシステム
JP3131918B2 (ja) メモリ装置
JPH063938B2 (ja) デ−タ転送バツフア方式
US7610452B1 (en) Data processing system wherein data is stored in a memory and an external storage in parallel
JP2551327B2 (ja) 実チップモデラ
JPH04107595A (ja) 表示システム
JPH0115070B2 (enrdf_load_html_response)
JPS5810945A (ja) デ−タ伝送装置
JPS61107285A (ja) デイスプレイ表示制御方式
JPH02207319A (ja) 端末制御方式
JPH063937B2 (ja) デ−タ転送方式
JPS6213690B2 (enrdf_load_html_response)
JPS6143094A (ja) ネツトワ−クアクセスタイム可変方式
JPS6122814B2 (enrdf_load_html_response)