JPH02126499A - Microcomputer - Google Patents

Abstract

PURPOSE:To use a PROM for the title microcomputer having short execution time for one instruction by writing a latched write data signal and another write data signal corresponding to the next address is parallel. CONSTITUTION:A 0 address is inputted from a PROM writer to an address signal for writing, and 8-bit data are inputted from the PROM writer to the write data signal, respectively. When a write signal 6 becomes a '1' level, since the address signal 7 for writing has the 0 address and an even address, a write data latch 4 latches the write data signal 5. Next, the write signal 6 becomes a '0' level, a 1 address is inputted from the PROM writer to the signal 7, and the data corresponding to the 1 address are inputted to the signal 5. When the write signal 6 becomes the '1' level, since the signal 7 has the 1 address and an odd address, a writing circuit 2 stores the output signal of the latch 4 and the data signal 5 into a PROM 1 in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to a microcomputer incorporating a PROM.

[Conventional technology]

Conventionally, some microcomputers have a built-in read-only memory (hereinafter referred to as ROM) for storing data such as instructions.

However, in microcomputers and the like constructed with one chip, the contents of the PROM are stored at the manufacturing stage, so the contents of the ROM cannot be changed after the product is completed. There is a microcomputer that has a built-in electrically programmable read-only memory (hereinafter referred to as PROM) so that the contents of the ROM can be changed after the product is completed. In order to store data in a microcomputer with a built-in PROM, a dedicated writing device (hereinafter referred to as PR) is required.
OM writer) is used. Generally PROM
The bit length of one address of data handled by a writer is 8 bits, but some microcomputers have a bit length of one instruction of 9 bits or more. A microcomputer in which one instruction is 9 bits or more requires means for converting 8-bit data into 9-bit or more data. Conventionally, for this purpose, PROM has configured the bit length of one address to be 8 bits, and stores the data from the PROM writer as is, and when reading it, PROM data of multiple addresses are read before executing one instruction, and this, etc. The data for one instruction was created by combining the data.

FIG. 2 is a block diagram showing a PROM section of a microcomputer incorporating a PROM in which the bit length of one instruction is 16 bits and the bit length of l address is 8 bits. below,
The operation will be explained with reference to FIG. When storing data in the PROM, the write data signal 13 receives 8-bit data from the PROM writer. The write signal has a value indicating write permission, for example, level “1”,
The write circuit PRs the data of the write data signal 13.
Store in OMI O. Next, the write signal becomes a value indicating write inhibition, for example, the "0" level, and data to be stored at the next address is input to the write data signal 13. PROMIO accesses the next address, repeats the same operation, and writes the data from the PROM writer.
Store it in ROMIO. After data is stored in PROMIO, when the microcomputer operates with this data, the read signal 15 becomes, for example, "1" level, and the read circuit 12 outputs the 8-bit data of PROMIO. First, the internal timing signal 16 is “
0" level, and the read data latch 17 latches the 8-bit output data of the read circuit 12. When the internal timing signal 16 changes from the "0" level to the "1" level, the read data latch 17 enters the holding state,
It holds data when the internal timing signal 16 is at "O" level. PROMI O accesses the next address and outputs data through the read circuit 12. The command register 18 takes in 16 bits of data including the 8 bits of the output signal of the read data latch 17 and the 8 bits of the output signal of the read circuit 12. That is, the internal timing signal 16 is set to "0" level -1 in the instruction register 18.
? The 16-bit data of the data read from the PROM and the data read from the PROM when the internal timing signal 16 is at the "1" level are taken in.

In this way, conventionally, when storing data, 8 bits of data from the PROM writer were stored as is in PROMIO, and when reading data, data at 2 addresses was read from PROMlo using the internal timing signal 16 to create 18,016 bits of data in the instruction register.

[Problem to be solved by the invention]

In the conventional microcomputer described above, it is necessary to read two addresses from the PROM in order to arrange the data for one instruction, so the execution time for one instruction needs to be longer than the time to read two addresses from the PROM. Therefore, it has the disadvantage that it cannot be used in micro combinators whose execution time for one instruction is short.

[Means to solve the problem]

The microfun computer of the present invention has a write data latch that latches a write data signal using a write signal and a write address signal, and a write data signal and an output signal of the write data latch that are connected to a PROM in parallel by a write signal and a write address signal. It has a write circuit for storing data in the memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram of a PROM section of a microcomputer showing one embodiment of the present invention. PROMI
is a PROM whose l address bit length is 16 bits for storing instruction data, and the write circuit 2 is configured so that the write signal 6 is “
When the write address signal 7 indicates an odd number 7 address at the 1'' level, the write circuit and read circuit 3 write the output signal of the write data latch 4 and the write data signal 5 to PROMI in parallel, and the read signal 8 is at the “1” level. The read circuit that reads PROMI data and outputs the data to the instruction register when , the write data latch 4 latches the write data signal 5 when the write signal 6 is at the "1" level and the write address signal 7 indicates an even address. latch circuit, write data signal 5
is an 8-bit data signal input from the PROM writer in response to write address signal 7.

The data write operation in FIG. 1 will be explained below. First, address 0 is entered into the write address signal from the PROM writer, and address 0 is entered into the write data signal from the PROM writer.
8-bit data is input from the M writer. When the write signal 6 reaches a value indicating write permission, for example, "1" level, the write data latch 4 latches the write data signal 5 because the write address signal 7 is at address 0 and an even address. Next, the write signal goes to the "0" level, a value that inhibits writing, and the address 1 from the PROM writer is entered into the write address signal 7, and the data corresponding to the address 1 is entered into the write data signal 5. When the write signal goes to the "1" level, the write address signal 7 is at address 1 and an odd address, so the write circuit 2 stores the output signal of the write data latch 4 and the write data signal 5 in parallel in PROMI. In other words, the 8-bit data at PROM writer address 0, which is latched in write data latch 4, and the 8-bit data at PROM writer address 1, which is included in write data signal 5, are stored in parallel as 16-bit data in PROMI. be done. Similarly, the 8-bit data at the PROM writer address 2 is latched by the write data latch 4, and stored in PROMI in parallel with the 8-bit data at the PROM writer address 3 carried in the write data signal 5. By repeating this operation, 1 is assigned to one address of PROMI.
It can store 6-bit data.

In the case of reading, when the read signal 8 goes to the "1" level, the read circuit 3 reads 16-bit data from the PROM1 and outputs the data to the instruction register 9. Therefore, the data for one instruction is prepared just by reading one address from the PROM hole, so the execution time for one instruction is
It is sufficient if there is enough time to read out one address.

〔Effect of the invention〕

As explained above, the present invention latches the write data signal in the write data latch using the write signal and write address signal, and writes the write data signal corresponding to the next address and the output signal of the write data latch in parallel. , the bit length of one address of the PROM can be made 9 bits or more, and the execution time of one instruction of the microcomputer can be reduced to the time required to read one address from the PROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the present invention, and FIG. 2 is a block diagram showing the conventional circuit configuration. 1...PROM, 2...Write circuit, 3...Read circuit, 4...Write data latch, 2...Write data signal, 6
...Write signal, 7...Write address signal, 8...Read signal, 9...
...Instruction register, 10...PROM. 11... Write circuit, 12... Read circuit, 13... Write data signal, 14
...Write signal, 15...Read signal, 16...mark/internal timing signal, 17...
...Read data latch, 18...Instruction register.

Claims (1)

[Claims] In a microcomputer with a built-in PROM, a write data latch latches a write data signal using a write signal and a write address signal;
A microcomputer including a write circuit that writes the write data signal and the output signal of the write data latch in parallel.