JPH02124573U - - Google Patents
Info
- Publication number
- JPH02124573U JPH02124573U JP3280289U JP3280289U JPH02124573U JP H02124573 U JPH02124573 U JP H02124573U JP 3280289 U JP3280289 U JP 3280289U JP 3280289 U JP3280289 U JP 3280289U JP H02124573 U JPH02124573 U JP H02124573U
- Authority
- JP
- Japan
- Prior art keywords
- block
- test mode
- tested
- asic
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案を実施したＡＳＩＣのテスト・
モード設定回路の一例、第２図は本考案回路の動
作を表わすタイムチヤート、第３図は従来のＡＳ
ＩＣのテスト動作を説明するための図である。
１……ＡＳＩＣ、ＢＡ，ＢＢ，ＢＣ……回路ブ
ロツク、ＢＴ……テスト・ブロツク、ＭＡ，ＭＢ
……マルチプレクサ、ＦＦ１〜ＦＦｎ……フリツ
プ・フロツプ回路。
Figure 1 shows the ASIC test and implementation of this invention.
An example of a mode setting circuit, Fig. 2 is a time chart showing the operation of the circuit of the present invention, and Fig. 3 is a conventional AS
FIG. 3 is a diagram for explaining an IC test operation. 1...ASIC, BA, BB, BC...Circuit block, BT...Test block, MA, MB
...Multiplexer, FF1 to FFn...Flip-flop circuit.
Claims (1)
るＡＳＩＣに付加され、テスト・クロツクをトグ
ルさせて１個目の前記テストすべきブロツクから
所望するブロツクまで順次テスト・モードを設定
し、ｎ個目のブロツクがテスト・モードに設定さ
れた後に通常動作モードに戻すシフト・レジスタ
構成のＡＳＩＣのテスト・モード設定回路。 It is attached to an ASIC having n blocks to be tested (n is an integer), and by toggling the test clock, the test mode is set sequentially from the first block to be tested to the desired block, and the test mode is set sequentially from the first block to be tested to the desired block. A test mode setting circuit for an ASIC having a shift register configuration that returns a block to a normal operation mode after it is set to a test mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3280289U JPH0719016Y2 (en) | 1989-03-23 | 1989-03-23 | ASIC test mode setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3280289U JPH0719016Y2 (en) | 1989-03-23 | 1989-03-23 | ASIC test mode setting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02124573U true JPH02124573U (en) | 1990-10-15 |
| JPH0719016Y2 JPH0719016Y2 (en) | 1995-05-01 |
Family
ID=31535996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3280289U Expired - Lifetime JPH0719016Y2 (en) | 1989-03-23 | 1989-03-23 | ASIC test mode setting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719016Y2 (en) |
-
1989
- 1989-03-23 JP JP3280289U patent/JPH0719016Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719016Y2 (en) | 1995-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02124573U (en) | ||
| JP2722567B2 (en) | Test selection circuit | |
| JPH0216076U (en) | ||
| JPH01120677U (en) | ||
| JPS63181978U (en) | ||
| JPS59166294U (en) | electronic musical instruments | |
| JPS6385210U (en) | ||
| JPH01103097U (en) | ||
| JPS63171027U (en) | ||
| JPS6452320U (en) | ||
| JPS5953441U (en) | microprocessor | |
| JPS6176492U (en) | ||
| JPS60178818U (en) | exposure equipment | |
| JPH02138340U (en) | ||
| JPS5914068U (en) | Measuring device for integrated circuits for watches | |
| JPS6046532U (en) | exposure compensation device | |
| JPS581992U (en) | automatic rhythm playing device | |
| JPS63146772U (en) | ||
| JPS6183372U (en) | ||
| JPH0360087U (en) | ||
| JPS59168795U (en) | musical tone synthesis circuit | |
| JPS61122581U (en) | ||
| JPH03115875U (en) | ||
| JPS6319897U (en) | ||
| JPS5939499U (en) | Main memory error bit display circuit |