JPS6183372U - - Google Patents
Info
- Publication number
- JPS6183372U JPS6183372U JP16873684U JP16873684U JPS6183372U JP S6183372 U JPS6183372 U JP S6183372U JP 16873684 U JP16873684 U JP 16873684U JP 16873684 U JP16873684 U JP 16873684U JP S6183372 U JPS6183372 U JP S6183372U
- Authority
- JP
- Japan
- Prior art keywords
- reduction ratio
- signal
- image
- clock signal
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Editing Of Facsimile Originals (AREA)
Description
第１図は本考案を適用した画像処理装置の一実
施例を示すブロツク図、第２図は実施例の各部出
力信号波形を示す図である。
２…ビデオクロツク発生器、２０…周波数制御
回路、２００…メモリ、２０１…シフトレジスタ
、２０２…アンドゲート。
FIG. 1 is a block diagram showing an embodiment of an image processing apparatus to which the present invention is applied, and FIG. 2 is a diagram showing output signal waveforms of each part of the embodiment. 2...Video clock generator, 20...Frequency control circuit, 200...Memory, 201...Shift register, 202...AND gate.
Claims (1)
信号の周波数を設定し、このビデオクロツク信号
により画像のビツトパターン列を出力し、所望の
縮小比率の表示画像または印字画像を得る画像縮
小装置において、所望の縮小比率の値を記憶した
メモリと、縮小比率「１」に対応した周波数のマ
スタクロツク信号を発生するクロツク発振器と、
前記メモリに記憶された縮小比率の値のビツト数
に対応した記憶位置を有し、各記憶位置にセツト
された縮小比率のビツト信号を前記マスタクロツ
ク信号によつて順次シフトしてシリアル信号とし
て出力するシフトレジスタと、このシフトレジス
タから出力されるシリアル信号とマスタクロツク
信号との論理積信号を出力するアンドゲートとを
備え、このアンドゲートの出力信号を上記ビデオ
クロツク信号としたことを特徴とする画像縮小装
置。 An image reduction device that sets the frequency of a video clock signal in accordance with a desired image reduction ratio, outputs a bit pattern string of an image using this video clock signal, and obtains a display image or a printed image with a desired reduction ratio. , a memory storing a desired reduction ratio value, and a clock oscillator that generates a master clock signal with a frequency corresponding to the reduction ratio "1".
It has storage locations corresponding to the number of bits of the reduction ratio value stored in the memory, and sequentially shifts the reduction ratio bit signal set in each storage location by the master clock signal and outputs it as a serial signal. An image comprising a shift register and an AND gate that outputs an AND signal of a serial signal output from the shift register and a master clock signal, and an output signal of the AND gate is used as the video clock signal. Reduction device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16873684U JPS6183372U (en) | 1984-11-07 | 1984-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16873684U JPS6183372U (en) | 1984-11-07 | 1984-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183372U true JPS6183372U (en) | 1986-06-02 |
Family
ID=30726496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16873684U Pending JPS6183372U (en) | 1984-11-07 | 1984-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183372U (en) |
-
1984
- 1984-11-07 JP JP16873684U patent/JPS6183372U/ja active Pending
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