JPS61173989U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the display circuit of this invention, FIG. 2 is a flowchart showing the relationship between control timings in the display circuit of this invention shown in FIG. 1, and FIG. Figure 1
and 2 is the timing R in the display circuit of this invention.
An example of data stored in the OM4, Figure 1 Display cycle and image memory 11 read data, Figure 2
indicates data written to the image memory 11. In the drawing, 1 is a clock oscillator, 2 is a counter, 3 is an access latch circuit, 4 is a timing ROM, 5 is a timing latch circuit, and 6 is a P
/S converter, 7 is a display data latch circuit, 8 is a display address counter, 9 is a display address buffer, 10 is an address selector, 11 is an image memory, 12 is a display data buffer, 13 is an access address buffer shows.

Claims (1)

[Scope of utility model registration request] A display control unit including a bit map type image memory consisting of a refresh memory, an access latch means for latching an access request to the image memory, an access address buffer, a data buffer, a display address counter, a display data latch means, etc. In a raster scan type CRT display device which is controlled by a central control means such as a CPU, the counter determines the cycle time of the image memory and generates various timing signals within the cycle period; A timing RO that generates various control signals and timing signals necessary for display control by a combination of the output of the access latch means and the output of the counter.
M, and a timing signal latch means for latching the output of the timing ROM, and various control signals and signals in the display cycle/access cycle are provided according to the data written in the timing ROM.
A display circuit characterized in that it generates a timing signal.