JPS60161393U

JPS60161393U - display device

Info

Publication number: JPS60161393U
Application number: JP4865784U
Authority: JP
Inventors: 勉荒川
Original assignee: 三洋電機株式会社
Priority date: 1984-04-03
Filing date: 1984-04-03
Publication date: 1985-10-26

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案装置の１実施例のブロック図、第２図イ
９口、ハ、二は動作説明図、第３図は従　　−来装置の
ブロック図である。主な符号の説明、ＲＭｌ・・・第１メモリ、ＳＧ・・・
信号発生器、ＲＭ２・・・第２メモリ、ＤＰ・・・表示
器、■■・・・マルチプレクサ、ＬＡ□、　ＬＡ２・・
・第ｉ、１２ラツチ、ＥＮ・・・提供回路（エンコーダ
）。FIG. 1 is a block diagram of one embodiment of the device of the present invention, FIG. Explanation of main symbols, RMl...first memory, SG...
Signal generator, RM2...second memory, DP...indicator, ■■...multiplexer, LA□, LA2...
・I-th, 12th latch, EN...Providing circuit (encoder).

Claims

[Scope of utility model registration request]

a first memory capable of storing image information to be displayed on the screen of a display device having a screen capable of displaying color information; a synchronization signal for scanning the display device; a first memory address assigned to the first memory; a signal generator for generating a clock signal; a first memory section designated by the first memory address; A second memory storing the color information addressed and specified by the stored second memory address.
a second memory comprising a memory section; a multiplexer for selectively assigning the first and second memory addresses to the second memory in accordance with the clock signal; and a second memory of the second memory; First and second latches each latching an address and the color information under the control of the clock signal, and receiving the second latch output and the first memory output, display the color information on the display. a circuit for providing the given image information.