JPS6452320U - - Google Patents
Info
- Publication number
- JPS6452320U JPS6452320U JP14760387U JP14760387U JPS6452320U JP S6452320 U JPS6452320 U JP S6452320U JP 14760387 U JP14760387 U JP 14760387U JP 14760387 U JP14760387 U JP 14760387U JP S6452320 U JPS6452320 U JP S6452320U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- dividing
- frequency divider
- frequency
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の分周装置の一実施例を示した
ブロツク図、第２図は第１図に示した分周装置の
テスト時の動作タイムチヤート、第３図は従来の
分周装置の一例を示したブロツク図、第４図は第
３図に示した分周装置の動作タイムチヤートであ
る。
１１〜１６……フリツプフロツプ、２……テス
ト回路。
Fig. 1 is a block diagram showing an embodiment of the frequency dividing device of the present invention, Fig. 2 is an operation time chart during testing of the frequency dividing device shown in Fig. 1, and Fig. 3 is a conventional frequency dividing device. FIG. 4 is a block diagram showing an example of this, and FIG. 4 is an operation time chart of the frequency dividing device shown in FIG. 1 1 to 1 6 . . . flip-flop, 2 . . . test circuit.
Claims (1)
回路の第１段目にクロツクを入力して最終段から
前記クロツクの分周信号を得る分周装置において
、テスト時に前記分周回路を少なくとも２つ以上
のブロツクに分割する分割手段と、前記分割手段
によつて分割された各ブロツクに前記クロツクを
供給する信号供給手段と、前記分割手段が所定周
期分の前記クロツクを前記各ブロツクに供給する
と前記各ブロツクを接続して元の分周回路を形成
する接続手段とを具備したことを特徴とする分周
装置。 In a frequency divider that inputs a clock to the first stage of a frequency divider circuit formed by connecting a plurality of unit frequency divider circuits and obtains a divided signal of the clock from the final stage, the frequency divider circuit is connected during testing. dividing means for dividing the clock into at least two or more blocks; signal supply means for supplying the clock to each block divided by the dividing means; and the dividing means supplies the clock for a predetermined period to each block. A frequency dividing device characterized in that it comprises connecting means which, when supplied, connects each of the blocks to form the original frequency dividing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14760387U JPS6452320U (en) | 1987-09-29 | 1987-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14760387U JPS6452320U (en) | 1987-09-29 | 1987-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6452320U true JPS6452320U (en) | 1989-03-31 |
Family
ID=31418159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14760387U Pending JPS6452320U (en) | 1987-09-29 | 1987-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6452320U (en) |
-
1987
- 1987-09-29 JP JP14760387U patent/JPS6452320U/ja active Pending
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