JPS6065696U - Electronic clock frequency adjustment device - Google Patents
Electronic clock frequency adjustment deviceInfo
- Publication number
- JPS6065696U JPS6065696U JP15961583U JP15961583U JPS6065696U JP S6065696 U JPS6065696 U JP S6065696U JP 15961583 U JP15961583 U JP 15961583U JP 15961583 U JP15961583 U JP 15961583U JP S6065696 U JPS6065696 U JP S6065696U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- circuit
- frequency divider
- output
- divider circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electric Clocks (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来の電子時計を示すブロック回路図。第２
図ａ、 ｂは、第１図の回路を示すタイムチャート図。
第３図は、本考案の一実施例を示すブロック回路図。第
４図は、第３図の動作を示すタイムチャート図。
２・・・基準信号発生器、４・・・分周回路、８・・・
エクスクル−シブオアゲート、１４・・・付加分周回路
、１６・・・周波数可変回路、２０・・・外部スイッチ
回路、３０・・・ラッチ回路。FIG. 1 is a block circuit diagram showing a conventional electronic timepiece. Second
Figures a and b are time charts showing the circuit of Figure 1. FIG. 3 is a block circuit diagram showing an embodiment of the present invention. FIG. 4 is a time chart diagram showing the operation of FIG. 3. 2... Reference signal generator, 4... Frequency dividing circuit, 8...
Exclusive OR gate, 14... Additional frequency dividing circuit, 16... Frequency variable circuit, 20... External switch circuit, 30... Latch circuit.
Claims (1)
基準周波数を分周する分周回路と、分周回路の出力によ
り時刻を表示する計時機構と、分周回路の出力をさらに
分周する付加分周回路と、分周回路の間に挿入された少
なくとも１個の排他的論理和回路と、付加分周回路の出
力を所望の排他的論理和回路に選択供給して前記分周回
路からの出力周波数を可変させる周波数可変回路と、前
記周波数可変回路の動作を外部から制御する外部スイッ
チ群と、から成る電子時計において、入力信号を一時的
に保持する複数個のラッチ回路を設け、前記複数個のラ
ッチ回路の出力を前記付加分周回路の出力の代わりに前
記周波数可変回路に入力させ、さらにこの複数個のラッ
チ回路は前記付加分周回路の１つの周波数信号が入力し
該周波数信号より低次の複数個の周波数信号によって各
ラッチ回路の保持をそれぞれ異なった時間に解除するよ
うに構成されたことを特徴とする電子時計の周波数調整
装置。A reference signal generator that generates a reference frequency signal for time, a frequency divider circuit that divides the reference frequency, a timekeeping mechanism that displays the time based on the output of the frequency divider circuit, and a frequency divider that further divides the output of the frequency divider circuit. an additional frequency divider circuit, at least one exclusive OR circuit inserted between the frequency divider circuits, and an output of the additional frequency divider circuit is selectively supplied to a desired exclusive OR circuit from the frequency divider circuit. An electronic timepiece comprising a frequency variable circuit that varies the output frequency of the frequency variable circuit, and a group of external switches that externally controls the operation of the frequency variable circuit. The outputs of a plurality of latch circuits are input to the frequency variable circuit instead of the output of the additional frequency divider circuit, and the plurality of latch circuits receive one frequency signal of the additional frequency divider circuit and input the frequency signal. 1. A frequency adjustment device for an electronic timepiece, characterized in that the holding of each latch circuit is released at different times using a plurality of lower-order frequency signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15961583U JPS6065696U (en) | 1983-10-14 | 1983-10-14 | Electronic clock frequency adjustment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15961583U JPS6065696U (en) | 1983-10-14 | 1983-10-14 | Electronic clock frequency adjustment device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6065696U true JPS6065696U (en) | 1985-05-09 |
| JPS6227912Y2 JPS6227912Y2 (en) | 1987-07-17 |
Family
ID=30351308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15961583U Granted JPS6065696U (en) | 1983-10-14 | 1983-10-14 | Electronic clock frequency adjustment device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6065696U (en) |
-
1983
- 1983-10-14 JP JP15961583U patent/JPS6065696U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6227912Y2 (en) | 1987-07-17 |
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